ST72561J6 STMicroelectronics, ST72561J6 Datasheet - Page 58

• Manufacturer Part Number: ST72561J6
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
WINDOW WATCHDOG (Cont’d)
10.1.9 Interrupts
None.
10.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read / Write
Reset Value: 0111 1111 (7F h)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
Figure 38. Watchdog Timer Register Map and Reset Values
58/265
WDGA
Address
(Hex.)
7
2F
30
T6
Reset Value
Reset Value
Register
WDGWR
WDGCR
Label
T5
T4
WDGA
7
T3
0
0
-
T2
W6
T6
6
1
1
T1
OSC2
T0
0
cy-
W5
T5
5
1
1
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be com-
pared to the downcounter.
W4
T4
7
-
4
1
1
W6
W3
T3
3
1
1
W5
W4
W2
T2
2
1
1
W3
W1
W2
T1
1
1
1
W1
W0
T0
0
1
1
W0
0