ST7263BE2 STMicroelectronics, ST7263BE2 Datasheet - Page 69

• Manufacturer Part Number: ST7263BE2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BE2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
Note:
1
2
3
4
5
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t = Pulse period (in seconds)
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t = Pulse period (in seconds)
f
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (See
The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate
an output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the One Pulse mode.
Figure 38. One Pulse mode timing example
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
CPU
EXT
= External timer clock frequency (in hertz)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see
COUNTER
OCMP1
ICAP1
IC1R
01F8
FFFC FFFD FFFE
Doc ID 7516 Rev 8
OCiR Value =
OLVL2
OCiR =
t
*
Figure
01F8
f
EXT
PRESC
t
*
f
compare1
CPU
2ED0 2ED1 2ED2
-5
38).
- 5
OLVL1
2ED3
FFFC FFFD
2ED3
On-chip peripherals
OLVL2
Table
24)
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