ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet
ST7263BK1
Specifications of ST7263BK1
Related parts for ST7263BK1
ST7263BK1 Summary of contents
Page 1
... HID and DFU software layers Table 1. Device summary Reference ST7263BHx ST7263BH2, ST7263BH6 ST7263BDx ST7263BD6 ST7263BK1, ST7263BK2, ST7263BKx ST7263BK4, ST7263BK6 ST7263BE1, ST7263BE2, ST7263BEx ST7263BE4, ST7263BE6 Doc ID 7516 Rev 8 LQFP48 (7x7 QFN40 (6x6) ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
ST7263Bxx 6.2.1 6.2.2 7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.3 Serial communications interface (SCI ...
Page 5
ST7263Bxx 12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Contents 13.11 8-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
ST7263Bxx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
List of tables Table 49. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
ST7263Bxx List of figures Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
List of figures Figure 49. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
ST7263Bxx 1 Introduction The ST7263B microcontrollers form a sub-family of the ST7 MCUs dedicated to USB applications. The devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They operate MHz or 12 ...
Page 12
Introduction Figure 1. General block diagram OSCIN OSCOUT RESET V PP/TEST ADC channels 48-pin devices (Port B and Port D[3:0 and 32-pin devices (Port B) None on 24-pin devices ...
Page 13
ST7263Bxx 2 Pin description 2.1 RESET signal (bidirectional active low and forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the ...
Page 14
Pin description Figure 2. 48-pin LQFP pinout USBOE/PC2 14/186 SSA USBDP 2 USBDM 3 USBV DDA OSCOUT 7 OSCIN ...
Page 15
ST7263Bxx Figure 3. 40-lead QFN package pinout PA0/MCO USBDP USBDM USBV OSCOUT 1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should not be connected ...
Page 16
Pin description Figure 4. 34-pin SO package pinout AIN7/IT8/PB7(10mA) AIN6/PB6/IT7(10mA) AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1(10mA) Figure 5. 32-pin SDIP package pinout AIN7/IT8/PB7(10mA) AIN6/IT7/PB6(10mA) AIN5/IT6/PB5(10mA) AIN4/IT5/PB4(10mA) AIN3/PB3(10mA) AIN2/PB2(10mA) AIN1/PB1/(10mA) Figure 6. 24-pin SO package pinout 16/186 ...
Page 17
ST7263Bxx Legend / Abbreviations for Type input output supply In/Output level:C T Output level 10mA high sink (Fn N-buffer only very high sink (on N-buffer only) ...
Page 18
Pin description Table 3. Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued) Pin n° Pin name PB2/AIN2 PB1/AIN1 PB0/AIN0 PA7/OCMP2/IT4 ...
Page 19
ST7263Bxx Table 3. Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued) Pin n° Pin name ( USBVCC DDA 1. Port D functions are not available on the 8 Kbyte version ...
Page 20
Pin description Table 4. Device pin description (SO24) Pin n° Pin name 20 PA0/MCO 21 V SSA 22 USBDP 23 USBDM 24 USBVCC 20/186 (continued) Level Port /control Input I I/O I/O O Doc ID 7516 Rev ...
Page 21
ST7263Bxx 3 Register and memory map As shown in Figure registers. The available memory locations consist 1024 bytes of RAM including 64 bytes of register locations, and up to 32K bytes of user program memory in which ...
Page 22
Register and memory map Table 6. Hardware register memory map Address Block Register label 0000h PADR Port A 0001h PADDR 0002h PBDR Port B 0003h PBDDR 0004h PCDR Port C 0005h PCDDR 0006h PDDR Port D 0007h PDDDR 0008h ITC ...
Page 23
ST7263Bxx Table 6. Hardware register memory map (continued) Address Block Register label 0025h USBPIDR 0026h USBDMAR 0027h USBIDR 0028h USBISTR 0029h USBIMR 002Ah USBCTLR 002Bh USB USBDADDR 002Ch USBEP0RA 002Dh USBEP0RB 002Eh USBEP1RA 002Fh USBEP1RB 0030h USBEP2RA 0031h USBEP2RB 0032h ...
Page 24
Flash program memory 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte ...
Page 25
ST7263Bxx 4.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level ...
Page 26
... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see to the device pinout description ...
Page 27
ST7263Bxx 4.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This ...
Page 28
Central processing unit 5 Central processing unit 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ...
Page 29
ST7263Bxx Condition Code register (CC) Reset value: 111x1xxx The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by ...
Page 30
Central processing unit Bit 2 N Negative This bit is set and cleared by hardware representative of the result sign of the last arithmetic, logical or data manipulation copy of the 7 0: The result ...
Page 31
ST7263Bxx pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 10. ● When an interrupt is received, the SP is decremented and the context is pushed on the stack. ● ...
Page 32
Reset and clock management 6 Reset and clock management 6.1 Reset The Reset procedure is used to provide an orderly software start- exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog ...
Page 33
ST7263Bxx Figure 12. Low voltage detector functional diagram Figure 13. Low Voltage Reset signal output 1. Hysteresis (V -V IT+ Figure 14. Temporization timing diagram after an internal Reset V DD Addresses LOW VOLTAGE V DD DETECTOR FROM WATCHDOG RESET ...
Page 34
Reset and clock management Figure 15. Reset timing diagram t DDR V DD OSCIN t OXOV f CPU PC RESET WATCHDOG RESET 1. Refer to Electrical Characteristics for values of t 34/186 FFFF FFFE 4096 CPU CLOCK CYCLES DELAY , ...
Page 35
ST7263Bxx 6.2 Clock system 6.2.1 General description The MCU accepts either a crystal or ceramic resonator external clock signal to drive the internal oscillator. The internal clock (f frequency (f ), which is divided by 3 (and by ...
Page 36
Reset and clock management Figure 17. Crystal/ceramic resonator Figure 18. Clock block diagram 36/186 OSCOUT OSCIN OSCIN % MHz %2 Crystal OSC24/12 Doc ID 7516 Rev 8 C OSCOUT ...
Page 37
ST7263Bxx 7 Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in processing flowchart is shown in The maskable interrupts must be enabled clearing the I bit in order to be ...
Page 38
Interrupts Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ● The I bit of the CC register is cleared. ● The corresponding enable bit is set ...
Page 39
ST7263Bxx Table 9. Interrupt mapping N° Source block RESET Reset TRAP Software interrupt FLASH Flash Start Programming interrupt USB End Suspend mode 1 ITi External interrupts 2 TIMER Timer Peripheral interrupts 3 I²C I²C Peripheral interrupts 4 SCI SCI Peripheral ...
Page 40
Power saving modes 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a Reset, the normal operating ...
Page 41
ST7263Bxx Figure 20. Halt mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 8.3 Slow mode In Slow ...
Page 42
Power saving modes The MCU will remain in Wait mode until a Reset or an interrupt occurs, causing it to wake up. Refer to Figure Related documentation AN 980: ST7 Keypad Decoding Techniques, Implementing Wakeup on Keystroke AN1014: How to ...
Page 43
ST7263Bxx 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins ● Analog signal input (ADC) ● Alternate signal input/output for the on-chip peripherals ● ...
Page 44
I/O ports Output mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin ...
Page 45
ST7263Bxx 9.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC input or true open drain. 9.3.1 Port A Table 11. ...
Page 46
I/O ports Table 12. PA1, PA2 description Port A 1 Input PA1 without pull-up PA2 without pull-up 1. Reset state. Figure 23. PA1, PA2 configuration LATCH DDR LATCH DDR SEL DR SEL 46/186 ( Output Very high ...
Page 47
ST7263Bxx 9.3.2 Port B Table 13. Port B description Port B Input PB0 without pull-up PB1 without pull-up PB2 without pull-up PB3 without pull-up PB4 without pull-up PB5 without pull-up PB6 without pull-up PB7 without pull-up 1. Reset State 2. ...
Page 48
I/O ports Figure 24. Port B and D[3:0] configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL ALTERNATE INPUT 48/186 ALTERNATE ENABLE 1 0 ALTERNATE ENABLE ANALOG ENABLE (ADC) 1 ALTERNATE ENABLE DIGITAL ENABLE 0 Doc ID 7516 ...
Page 49
ST7263Bxx 9.3.3 Port C Table 14. Port C description Port C (1) Input PC0 with pull-up PC1 with pull-up (2) PC2 with pull-up 1. Reset state 2. Not available on SO24 Figure 25. Port C configuration ALTERNATE OUTPUT DR LATCH ...
Page 50
I/O ports 9.3.4 Port D Table 15. Port D description Port D (1) Input PD0 without pull-up PD1 without pull-up PD2 without pull-up PD3 without pull-up PD4 with pull-up PD5 with pull-up PD6 with pull-up PD7 with pull-up 1. Reset ...
Page 51
ST7263Bxx . 7 D7 [7:0] D[7:0] Data register 8 bits. Data Direction register (PxDDR) Address Port A Data Direction register (PADDR): 0001h Port B Data Direction register (PBDDR): 0003h Port C Data Direction register (PCDDR): 0005h Port D Data Direction ...
Page 52
I/O ports 9.3.6 Related documentation AN1045: S/W implementation of I AN1048: Software LCD driver 52/186 2 C bus master Doc ID 7516 Rev 8 ST7263Bxx ...
Page 53
ST7263Bxx 10 Miscellaneous register Miscellaneous register (MISCR) Address: 0009h Reset value: 0000 0000 (00h Read/write [7:3] Reserved 2 SMS Slow mode Select. This bit is set by software and only cleared by hardware after a ...
Page 54
On-chip peripherals 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to ...
Page 55
ST7263Bxx Figure 26. Watchdog block diagram f CPU a Table 17. Watchdog timing (f CR register initial value Max Min Note: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 ...
Page 56
On-chip peripherals HALT instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). Using Halt mode with the WDG (option) ...
Page 57
ST7263Bxx 11.1.8 Register description Control register (CR) Reset value: 0111 1111 (7Fh) 7 WDGA 7 WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate ...
Page 58
On-chip peripherals 11.2 16-bit timer 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input ...
Page 59
ST7263Bxx 11.2.3 Functional description Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. ● Counter register ...
Page 60
On-chip peripherals Figure 27. Timer block diagram f CPU 8 high EXEDG 1/2 1/4 1/8 EXTCLK pin CC[1:0] OVERFLOW ICF1 OCF1 TOF ICIE OCIE TOIE (See note) TIMER INTERRUPT 1. If IC, OC and TO interrupt requests have separate vectors ...
Page 61
ST7263Bxx Figure 28. 16-bit read sequence (from either the Counter register or the Alternate Counter register) The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit ...
Page 62
On-chip peripherals A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure ...
Page 63
ST7263Bxx Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value ...
Page 64
On-chip peripherals Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which ...
Page 65
ST7263Bxx Output Compare In this section, the index, i, may because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period ...
Page 66
On-chip peripherals = Timer prescaler factor ( depending on CC[1:0] bits, see PRESC If the timer clock is an external clock, the formula is: Where: Δ Output compare period (in seconds External timer ...
Page 67
ST7263Bxx Figure 34. Output Compare block diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R register OC2R register Figure 35. Output Compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) Figure ...
Page 68
On-chip peripherals One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the input Capture1 function ...
Page 69
ST7263Bxx The OC1R register value required for a specific timing application can be calculated using the following formula: Where Pulse period (in seconds CPU clock frequency (in hertz) CPU = Timer prescaler factor ( ...
Page 70
On-chip peripherals Figure 39. Pulse Width modulation mode timing with 2 output Compare functions COUNTER 34E2 OCMP1 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 On timers with only one output Compare register, a fixed ...
Page 71
ST7263Bxx Figure 40. Pulse width modulation cycle If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be seen ...
Page 72
On-chip peripherals 11.2.4 Low power modes a Table 21. Low power modes Mode WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from Wait mode. 16-bit Timer registers are frozen. In Halt mode, the counter stops ...
Page 73
ST7263Bxx 11.2.7 Register description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control ...
Page 74
On-chip peripherals Control register 2 (CR2) Reset value: 0000 0000 (00h) 7 OC1E OC2E [3: 74/186 OPM PWM Read/write OC1E output Compare 1 Pin Enable. This bit is used only to output the signal ...
Page 75
ST7263Bxx Table 24. Clock Control bits External Clock (where available) Control/status register (CSR) Reset value: xxxx x0xx (xxh) 7 ICF1 OCF1 7 ICF1 input Capture Flag input capture (reset value input capture has occurred on ...
Page 76
On-chip peripherals 3 OCF2 output Compare Flag match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read ...
Page 77
ST7263Bxx 7 MSB Output Compare 2 High register (OC2HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Output Compare 2 Low ...
Page 78
On-chip peripherals 7 MSB Alternate Counter Low register (ACLR) Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this ...
Page 79
ST7263Bxx Table 25. 16-bit timer register map and reset values Address Register 7 label (Hex.) CR2 OC1E 11 Reset value 0 CR1 ICIE 12 Reset value 0 CSR ICF1 13 Reset value 0 IC1HR 14 MSB Reset value IC1LR 15 ...
Page 80
On-chip peripherals 11.3 Serial communications interface (SCI) 11.3.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide ...
Page 81
ST7263Bxx Through these pins, serial data is transmitted and received as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word ( bits) least significant bit first ● A ...
Page 82
On-chip peripherals 11.3.4 Functional description The block diagram of the Serial Control Interface, is shown in dedicated registers: ● Two control registers (SCICR1 & SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) Refer to the register ...
Page 83
ST7263Bxx Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be ...
Page 84
On-chip peripherals As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame ...
Page 85
ST7263Bxx When a overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the ...
Page 86
On-chip peripherals Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with (see SCP[1:0] bits ...
Page 87
ST7263Bxx Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible ...
Page 88
On-chip peripherals clock occurs just before the pin value changes, the samples would then be out of sync by ~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample + ...
Page 89
ST7263Bxx Figure 43. Bit sampling in reception mode RDI LINE Sample clock 1 11.3.5 Low power modes Table 27. Low power modes Mode WAIT HALT 11.3.6 Interrupts Table 28. Interrupts Interrupt event Transmit Data register Empty Transmission Complete Received Data ...
Page 90
On-chip peripherals 11.3.7 Register description Status register (SCISR) Reset value: 1100 0000 (C0h) 7 TDRE TC 7 TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the ...
Page 91
ST7263Bxx 3 OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the ...
Page 92
On-chip peripherals Control register 1 (SCICR1) Reset value: x000 0000 (x0h Receive data bit Transmit data bit 8. 5 SCID Disabled for low power consumption 4 M Word length. 3 WAKE Wakeup ...
Page 93
ST7263Bxx Control register 2 (SCICR2) Reset value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE Read/write 7 TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever ...
Page 94
On-chip peripherals Data register (SCIDR) Reset value: Undefined This register contains the received or transmitted data character, depending on whether it is read from or written to. 7 DR7 DR6 The Data register performs a double function (read and write) ...
Page 95
ST7263Bxx Baud Rate register (SCIBRR) Reset value: 0000 0000 (00h) 7 SCP1 SCP0 [7:6] SCP[1:0] First SCI Prescaler [5:3] SCT[2:0] SCI Transmitter rate divisor [2:0] SCR[2:0] SCI Receiver rate divisor. Table 29. Prescaling factors PR prescaling factor . Table 30. ...
Page 96
On-chip peripherals Table 31. RR dividing factor RR dividing factor Table 32. SCI register map and reset values Address Register (Hex.) label SCISR 20 Reset value SCIDR 21 Reset value SCIBRR 22 Reset value SCICR1 23 Reset value SCICR2 24 ...
Page 97
ST7263Bxx 11.4 USB interface (USB) 11.4.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external ...
Page 98
On-chip peripherals Figure 44. USB block diagram USBDM USBDP USBVCC USBGND 11.4.4 Register description DMA Address register (DMAR) Reset value: undefined 7 DA15 DA14 [7:0] DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory ...
Page 99
ST7263Bxx Interrupt/DMA register (IDR) Reset value: xxxx 0000 (x0h) 7 DA7 DA6 [7:6] DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure [5:4] EP[1:0] Endpoint number (read-only). These bits identify ...
Page 100
On-chip peripherals PID register (PIDR) Reset value: xx00 0000 (x0h) 7 TP3 TP2 [7:6] TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. ...
Page 101
ST7263Bxx Interrupt Status register (ISTR) Reset value: 0000 0000 (00h) 7 SUSP DOVR When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits ...
Page 102
On-chip peripherals 2 ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to ...
Page 103
ST7263Bxx Control register (CTLR) Reset value: 0000 0110 (06h [7:4] Reserved. Forced by hardware RESUME Resume. This bit is set by software to wakeup the Host when the ST7 is in suspend mode. 0: ...
Page 104
On-chip peripherals Endpoint n register A (EPnRA) These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some ...
Page 105
ST7263Bxx Endpoint n register B (EPnRB) These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RB register are not ...
Page 106
On-chip peripherals Endpoint 0 register B (EP0RB) This register is used for controlling data reception on Endpoint also reset by the USB bus reset. Reset value: 1000 0000 (80h) 7 DTOG 1 7 Forced by hardware to ...
Page 107
ST7263Bxx Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly. When the operation is completed, they can be accessed again to ...
Page 108
On-chip peripherals Table 36. USB register map and reset values (continued) Address Register 7 Name (Hex.) IDR DA7 27 Reset x value ISTR SUSP 28 Reset 0 value IMR SUSPM 29 Reset 0 value CTLR 0 2A Reset 0 value ...
Page 109
ST7263Bxx 11.5 I²C bus interface 11.5.1 Introduction The I²C bus interface serves as an interface between the microcontroller and the serial I²C bus. It provides both multimaster and slave functions, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. ...
Page 110
On-chip peripherals Mode selection The interface can operate in the four following modes: ● Slave transmitter/receiver ● Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition ...
Page 111
ST7263Bxx When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. Figure 47. I²C interface block diagram SDA or SDAI SCL or SCLI 11.5.4 Functional description Refer to the CR, SR1 and ...
Page 112
On-chip peripherals Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ● Acknowledge ...
Page 113
ST7263Bxx Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent, the EVF and SB bits are set ...
Page 114
On-chip peripherals each 9-bit transaction: Single Master mode If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag ...
Page 115
ST7263Bxx Figure 48. Transfer sequencing Table 37. Slave receiver Addres Table 38. Slave Transmitter Addres Table 39. Master receiver Addres Table 40. Master Transmitter Addres ...
Page 116
On-chip peripherals 11.5.5 Low power modes Table 41. Low power modes Mode No effect on I²C interface. WAIT I²C interrupts cause the device to exit from Wait mode. I²C registers are frozen. In Halt mode, the I²C interface is inactive ...
Page 117
ST7263Bxx 11.5.7 Register description I²C Control register (CR) Reset value: 0000 0000 (00h [7:6] Reserved. Forced hardware Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability ...
Page 118
On-chip peripherals 2 ACK Acknowledge enable. This bit is set and cleared by software also cleared by hardware when the interface is disabled (PE=0 acknowledge returned 1: Acknowledge returned after an address byte or a data ...
Page 119
ST7263Bxx I²C Status register 1 (SR1) Reset value: 0000 0000 (00h) 7 EVF 7 EVF Event flag This bit is set by hardware as soon as an event occurs cleared by software reading SR2 register in case of ...
Page 120
On-chip peripherals 3 BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE= cleared by software reading SR1 register followed by a read ...
Page 121
ST7263Bxx I²C Status register 2 (SR2) Reset value: 0000 0000 (00h [7:5] Reserved. Forced hardware Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated ...
Page 122
On-chip peripherals 2 ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE= cleared by software reading SR2 register or by ...
Page 123
ST7263Bxx I²C Data register (DR) These bits contain the byte to be received or transmitted on the bus. ● Transmitter mode: byte transmission start automatically when the software writes in the DR register. ● Receiver mode: the first data byte ...
Page 124
On-chip peripherals Table 43. I²C register map Address Register name (Hex OAR 3C CCR 3D SR2 3E SR1 3F CR Note: Refer to Section 16: Known limitations function on pin PA2 (SCL). 124/186 ...
Page 125
ST7263Bxx 11.6 8-bit A/D converter (ADC) 11.6.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...
Page 126
On-chip peripherals Figure 50. ADC block diagram AIN0 AIN1 AINx Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If ...
Page 127
ST7263Bxx Software procedure Refer to the control/status register (CSR) and data register (DR) in definitions and to ADC configuration The total duration of the A/D conversion is 12 ADC clock periods (1/f The analog input ports must be configured as ...
Page 128
On-chip peripherals 11.6.5 Interrupts None 11.6.6 Register description Control/Status register (CSR) Reset value: 0000 0000 (00h) 7 COCO 7 COCO Conversion Complete This bit is set by hardware cleared by software reading the result in the DR register ...
Page 129
ST7263Bxx 2. For SDIP/SO34 devices, the CH3 bit is always at ‘0’. If, however, set to ‘1’ on error, channel (11:8) becomes enabled which may result in a higher and unnecessary level of consumption. Data register (DR) This register contains ...
Page 130
Instruction set 12 Instruction set 12.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Table 47. Addressing modes Addressing mode The ST7 Instruction set is designed to minimize the ...
Page 131
ST7263Bxx Table 48. ST7 addressing mode overview (continued) Mode Long Indirect Short Indirect Indexed Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the ...
Page 132
Instruction set Table 49. Inherent instructions (continued) Inherent instruction SLL, SRL, SRA, RLC, RRC 12.1.2 Immediate instructions Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Table 50. Immediate instructions Immediate ...
Page 133
ST7263Bxx Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes ...
Page 134
Instruction set Table 51. Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes (continued) Long and Short instructions Short Instructions only SLL, SRL, SRA, RLC, RRC 12.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the ...
Page 135
ST7263Bxx 12.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 53. Instruction groups Load and Transfer Stack operation ...
Page 136
Instruction set Table 54. Instructions Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true ...
Page 137
ST7263Bxx Table 54. Instructions (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from ...
Page 138
Electrical characteristics 13 Electrical characteristics 13.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 13.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
Page 139
ST7263Bxx Figure 53. Pin input voltage 13.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions ...
Page 140
Electrical characteristics Table 56. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) (2)(3) I INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly ...
Page 141
ST7263Bxx 13.3 Operating conditions Table 58. General operating conditions Symbol V Operating Supply Voltage DD V Analog reference voltage DDA V Analog reference voltage SSA f Operating frequency CPU T Ambient temperature range A Figure 54. f CPU f [MHz] ...
Page 142
Electrical characteristics 13.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values ...
Page 143
ST7263Bxx Figure 56. Typ. I 13.5 Clock and timing characteristics Subject to general operating conditions for V Table 61. General timings Symbol t Instruction cycle time c(INST) Interrupt reaction time t v(IT) = Δt t v(IT) 1. Data based on ...
Page 144
Electrical characteristics Table 62. Control timing characteristics t Watchdog timeout WDG t Crystal oscillator startup time OXOV t Power up rise time DDR 1. Not tested in production, guaranteed by characterization. Table 63. External clock source Symbol Parameter V OSCIN ...
Page 145
ST7263Bxx Figure 58. Typical application with a crystal resonator 13.6 Memory characteristics Subject to general operating conditions for f Table 64. RAM and hardware registers Symbol V Data retention mode RM 1. Guaranteed by design. Not ...
Page 146
Electrical characteristics Figure 59. Two typical applications with ST72XXX 1. When the ICP mode is not required by the application, V 146/186 pin PP PROGRAMMING TOOL pin must be tied Doc ID ...
Page 147
ST7263Bxx 13.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by ...
Page 148
Electrical characteristics 13.7.2 Electromagnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...
Page 149
... Electrical sensitivities Symbol LU Static latchup class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 13.8 ...
Page 150
Electrical characteristics Figure 61. Typ. I Figure 62. Typ. R 150/186 vs Pull-up current (µ 4.2 4.4 4.6 Vdd (V) vs Rpu (KOhm) ...
Page 151
ST7263Bxx Table 71. Output driving current Symbol Parameter Output low level voltage for a standard I/O pin when pins are sunk at the same time, Port A0, Port A(3:7), Port C(0:2), Port D(0:7) Output low level voltage ...
Page 152
Electrical characteristics Figure 64 Figure 65 152/186 high sink Vol_10mA (V) at Vdd=5V 1.6 1.4 1.2 1 0.8 0.6 0.4 0 Iio (mA) very high sink V =5 ...
Page 153
ST7263Bxx Figure 66 Figure 67 standard vs Vol_2mA (mV) at Iio=2mA 130 125 120 115 110 105 4 4.2 4.4 4.6 Vdd (V) high sink vs Vol_10mA (V) at Iio=10mA 0.6 0.59 ...
Page 154
Electrical characteristics Figure 68 Figure 69 0.25 0.15 0.05 154/186 very high sink vs Vol_25mA (V) at Iio=25mA 0.8 0.75 0.7 0.65 0.6 4 4.2 4.4 4.6 Vdd ( ...
Page 155
ST7263Bxx Figure 70 Figure 71 (high current |Vdd - Voh| (V) at Vdd=5V 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 -Iio (mA) ...
Page 156
Electrical characteristics Figure 72 13.9 Control pin characteristics Subject to general operating conditions for V Table 72. Asynchronous RESET pin Symbol Parameter V Input high level voltage IH V Input low voltage IL Schmitt trigger voltage V hys ...
Page 157
ST7263Bxx Figure 73 and Figure 74 resets: ● The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD ...
Page 158
Electrical characteristics Figure 74. RESET pin protection when LVD is disabled USER EXTERNAL RESET CIRCUIT 0.01μF Required 13.10 Communication interface characteristics 13.10.1 USB interface Operating conditions T Table 73. USB DC characteristics Symbol Parameter V Differential input sensitivity DI V ...
Page 159
ST7263Bxx Table 74. USB low-speed electrical characteristics Symbol Driver characteristics: t Rise time r t Fall Time f t Rise/ fall time matching rfm V Output signal crossover voltage CRS 1. For more detailed information, please refer to Chapter 7 ...
Page 160
Electrical characteristics 2 13.10 interface Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). 2 The ST7 I C interface meets the requirements of the standard I described in the ...
Page 161
ST7263Bxx Figure 76. Typical application with 4.7kΩ BUS START SDA t t r(SDA) f(SDA) SCK h(STA) w(SCKH) w(SCKL) 1. Measurement points are done at CMOS levels: 0.3xV 2 C bus and ...
Page 162
Electrical characteristics Table 77 gives the values to be written in the I2CCCR register to obtain the required I SCL line frequency. (1)(2)(3)(4) Table 77. SCL frequency f CPU f SCL (kHz 4 =3.3 kΩ ...
Page 163
ST7263Bxx Figure 77. Typical application with ADC V AIN V DD Table 79. ADC accuracy with V Symbol |E | Total unadjusted error T |E Offset error O| |E Gain Error Differential linearity error ...
Page 164
Electrical characteristics Figure 78. ADC accuracy characteristics Digital Result ADCDR 255 254 253 SSA 1. (1) Example of an actual transfer curve; (2) The ideal transfer curve; (3) End point correlation ...
Page 165
ST7263Bxx 14 Package characteristics In order to meet environmental requirements, ST offers this device in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ...
Page 166
Package characteristics 14.1 Package mechanical data Figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline b1 Table 80. 32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data Dim. Min A 3.560 A1 0.510 A2 3.050 ...
Page 167
ST7263Bxx Figure 80. 34-pin plastic small outline package, 300-mil width, package outline Table 81. 34-pin plastic small outline package, 300-mil width, package mechanical data Dim. Min A 2.464 A1 0.127 B 0.356 C 0.231 D 17.729 E 7.417 e H ...
Page 168
Package characteristics Figure 81. 24-pin plastic small outline package, 300-mil width package outline Table 82. 24-pin plastic small outline package, 300-mil width package mechanical data Dim. Min A 2.350 A1 0.100 B 0.330 C 0.230 ...
Page 169
ST7263Bxx Figure 82. 48-pin low profile quad flat package outline Pin 1 identification 1 Table 83. 48-pin low profile quad flat package mechanical data Dim. Min A A1 0.050 A2 1.350 b 0.170 c 0.090 D ...
Page 170
Package characteristics Figure 83. 40-lead very thin fine pitch quad flat no-lead package outline A SEATING PLANE PIN #1 ID TYPE C RADIUS L Table 84. 40-lead very thin fine pitch quad flat no-lead package mechanical data Dim. Min A ...
Page 171
ST7263Bxx 14.2 Thermal characteristics Table 85. Thermal characteristics Symbol R thJA Jmax 1. The maximum power dissipation is obtained from the formula application can be defined by the user with the formula: P internal ...
Page 172
... Reset generation when entering Halt mode OPT 3 LVD Low voltage detector selection This option bit selects the LVD. 0: LVD enabled 1: LVD disabled Note: Important: on ST7263BK1M1, ST7263BK2M1, ST7263BK2B1, and 172/186 WDG SW WD HALT LVD ST7263BK2B1 ROM devices, this option bit is forced (LVD always enabled) ...
Page 173
... The selected options are communicated to STMicroelectronics using the correctly completed option list appended (see Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 86. Supported order codes ...
Page 174
... ST72F63BE2M1 ST72F63BK1M1 ST72F63BK1B1 ST72F63BE1M1 ST7263BK2M1/xxx ST7263BK2B1/xxx ST7263BK1M1/xxx ST7263BK1B1/xxx 1. /xxx stands for the ROM code name assigned by STMicroelectronics. 2. Contact ST sales office for FASTROM product availability. 15.3 Development tools Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers ...
Page 175
ST7263Bxx environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface. 15.3.3 Programming tools During the development cycle, the ST7-EMU3 series emulators and the RLink provide in- circuit programming capability for programming the Flash microcontroller on your ...
Page 176
... For marking, one line is possible with a maximum of 13 characters. Watchdog Selection: Halt when Watchdog on: LVD Reset * * LVD is forced to 0 (LVD always enabled) for 4K and 8K ROM devices (sales types ST7263BK1B1, ST7263BK2B1, ST7263BK1M1, ST72BK2M1 only) Oscillator Selection: Readout Protection: Date . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 177
ST7263Bxx 15.4 ST7 application notes Table 88. ST7 application notes Identification Application examples AN1658 Serial Numbering Implementation AN1720 Managing the Readout Protection in Flash Microcontrollers AN1755 A High Resolution/precision Thermometer Using ST7 and NE555 AN1756 Choosing a DALI Implementation Strategy ...
Page 178
Device configuration and ordering information Table 88. ST7 application notes (continued) Identification AN1276 BLDC Motor Start Routine for the ST72141 Microcontroller AN1321 Using the ST72141 Motor Control MCU in Sensor mode AN1325 Using the ST7 USB LOW-SPEED Firmware V4.x AN1445 ...
Page 179
ST7263Bxx Table 88. ST7 application notes (continued) Identification AN1014 How to Minimize the ST7 Power Consumption AN1015 Software Techniques for Improving Microcontroller EMC Performance AN1040 Monitoring the Vbus Signal for USB Self-Powered Devices AN1070 ST7 Checksum Self-Checking Capability AN1181 Electrostatic ...
Page 180
Device configuration and ordering information Table 88. ST7 application notes (continued) Identification AN1635 ST7 Customer ROM Code Release Information AN1754 Data Logging Program for Testing ST7 Applications via I AN1796 Field Updates for FLASH Based ST7 Applications Using a PC ...
Page 181
... To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 16.3 USB behavior with LVD disabled Description If the LVD is disabled on 4K and 8K ROM devices (ST7263BK1M1, ST72BK2M1, ST7263BKB1, ST7263BK2B1 only), the USB is disabled by hardware. The LVD is consequently forced ‘0’ (LVD enabled). Refer to the ST7263Bx option list for details ...
Page 182
Known limitations 16.5 Halt mode power consumption with ADC on Description If the A/D converter is being used when Halt mode is entered, the power consumption in Halt mode may exceed the maximum specified in the datasheet. Workaround Switch off ...
Page 183
ST7263Bxx Figure 85. Identifying silicon revision from device marking and box label The silicon revision can be identified either by Rev letter or obtained via a trace code. 1. Identify the silicon revision letter from either the device package or ...
Page 184
Revision history 17 Revision history Table 89. Document revision history Date 27-May-05 19-Sep-05 06-Apr-06 184/186 Revision New revision created by merging 32K Flash and non-32K Flash datasheets together. Memory Map, devices and memory sizes. Operating conditions with LVD values modified, ...
Page 185
ST7263Bxx Table 89. Document revision history (continued) Date 03-Oct-06 20-Aug-07 12-Jun-2009 Revision Important Notes section renamed to Known Limitations, Known limitations 6 New PA2 limitation added, Figure 85 on page 183 New 16K LQFP48 package added to product family. Note ...
Page 186
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...