ST72325S6 STMicroelectronics, ST72325S6 Datasheet - Page 33
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ST72325S6
Manufacturer Part Number
ST72325S6
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST72325K4.pdf
(197 pages)
Specifications of ST72325S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
Figure 19. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
V
V
IT+(EVD)
IT-(EVD)
V
EVD
0
INTERRUPT PROCESS
V
hyst
1
of the comparator output. This means it is generat-
ed when either one of these two events occur:
The EVD function is illustrated in
For more details, refer to the Electrical Character-
istics section.
– V
– V
EVD
EVD
rises up to V
falls down to V
IT+(EVD)
IT-(EVD)
INTERRUPT PROCESS
Figure
0
ST72325xx
19.
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