STR751FR1 STMicroelectronics, STR751FR1 Datasheet
STR751FR1
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... Up to 72/38 I/O ports – 72/38 GPIOs with High Sink capabilities – Atomic bit SET and RES operations Table 1. Device summary Reference STR750Fxx STR750FV0, STR750FV1, STR750FV2 STR751Fxx STR751FR0, STR751FR1, STR751FR2 STR752Fxx STR752FR0, STR752FR1, STR752FR2 STR755FR0, STR755FR1, STR755FR2 STR755Fxx STR755FV0, STR755FV1, STR755FV2 Rev 5 LQFP100 LFBGA100 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Common Peripherals 38 I/Os 13 Wake-up lines, 11 A/D Channels USB/CAN peripherals None Operating Voltage 3. Packages (x) 4/84 STR750Fxx STR751Fxx STR752Fxx STR755Fxx STR751FR0/ STR752FR0/ STR751FR1/ STR752FR1/ STR751FR2 STR752FR2 64K/128K/256K 16K RWW Ambient temp.:-40 to +85°C / -40 to +105°C (see Junction temp. - 125 °C (see USB CAN 3.3V ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 3 Introduction This Datasheet contains the description of the STR750F family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750F Reference ...
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Introduction Serial memory interface (SMI) The Serial Memory interface is directly able to access serial FLASH devices. It can be used to access data, execute code directly or boot the application from external memory. The memory is ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx regulator and the V regulator. This scheme has the advantage of requiring only one 5.0V power source. ● Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are ...
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Introduction periodic interrupt clocked by an external 32.768 kHz oscillator or the internal low power RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated. WDG (watchdog timer) The watchdog timer is based ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx I²C bus The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). High speed universal asynch. receiver transmitter (UART) The three UART interfaces are able ...
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Introduction GPIOs (general purpose input/output) Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down Peripheral Alternate Function. Port ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 3.2 Block diagram Figure 1. STR750 block diagram BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF SCLK, MOSI MISO 15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC ...
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Pin description 4 Pin description Figure 2. LQFP100 pinout ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 3. LQFP64 pinout ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 UART2_TX / UART0_RTS / RTCK / P0. A/D input channels ...
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Pin description Table 4. LFBGA100 ball connections P0.03 P1.13 P1.14 B P1.12 P0.02 P0.01 C P0.31 P0. P0.29 P0. P0.28 P0.23 P0.22 F P2.03 P0.21 P0.20 G NJTRST P1.18 P1.19 H P0.13 P1.16 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 4.1 Pin description table Legend / abbreviations for Type: Input levels: Inputs: Outputs: External interrupts/wake-up lines: EITx Table input output supply, All Inputs are LVTTL at V ± at ...
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Pin description Port reset state The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions: ● The JTAG inputs (JTDI, JTMS and JTDI) are configured as input ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin name P0.29 / TIM1_TI1 ADC_IN8 P0. TIM1_OC1 TEST VSS_IO ...
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Pin description Table 6. STR750F pin description (continued) Pin n° Pin name P0.12 / UART2_RX / UART0_CTS / ADC_IN2 / SMI_CS1 P0.11 / UART0_TX / BOOT1 / SMI_CS2 P0. ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin name 43 H9 P2. VDD_IO VDDA_PLL XT2 XT1 48 J10 31 ...
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Pin description Table 6. STR750F pin description (continued) Pin n° Pin name P1. A10 TIM2_OC2 VDD_IO VDDA_ADC 71 C9 P2.11 72 B10 P2. VSSA_ADC 74 C7 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin name P1.04 / PWM3N / ADC_IN9 P1. ADC_IN15 P1. ADC_IN14 94 D5 P1.01 / TIM0_TI2 P1.00 / ...
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Pin description 4.2 External components Figure 4. Required external capacitors when regulators are used 97 V SS18 SS18 LFBGA100 22/84 STR750Fxx STR751Fxx STR752Fxx STR755Fxx 18BKP 18 1µ SSBKP ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5 Memory map Figure 5. Memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF APB TO ARM7 BRIDGE 0xFFFF 8000 7 0xE000 0000 0xDFFF FFFF 6 0xC000 0000 0xBFFF FFFF 5 0xA000 0000 0x9FFF FFFF 4 ...
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Electrical parameters 6 Electrical parameters 6.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Pin loading conditions 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in ...
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Electrical parameters 6.1.6 Power supply schemes When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below. Power supply scheme 1: Single external 3.3 V power source ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Power supply scheme 2: Dual external 1.8V and 3.3V supply Figure 9. Power supply scheme 2 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 3.3V +/-0.3V V SS_IO ...
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Electrical parameters Power supply scheme 3: Single external 5 V power source Figure 10. Power supply scheme 3 V 18_BKP 1µF V SS_BKP VREG_DIS V 18 33nF V SS18 V 18REG 10µF V SS18 V DD_IO 1µF 5.0V +/-0.5V V ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Power supply scheme 4: Dual external 1.8 V and 5.0 V supply Figure 11. Power supply scheme 4 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 5.0V +/-0.5V ...
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Electrical parameters Figure 12. Power consumption measurements in power scheme 1 (regulators enabled) 3.3V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 13. Power consumption measurements ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 14. Power consumption measurements in power scheme 3 (regulators enabled) 5.0V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 15. Power ...
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Electrical parameters 6.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.2.2 Current characteristics Table 8. Current characteristics Symbol (1) I VDD_IO (1) I VSS_IO I IO (3) & (4) I INJ(PIN) ΣI (3) INJ(PIN) 1. The user can use GPIOs to source or sink high current ...
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Electrical parameters 6.3 Operating conditions 6.3.1 General operating conditions Subject to general operating conditions for V Table 10. General operating conditions Symbol f Internal AHB Clock frequency HCLK f Internal APB Clock frequency PCLK Standard Operating Voltage Power Scheme 1 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for T Table 11. Operating conditions at power-up / power-down Symbol Parameter t V VDD_IO DD_IO t V rise time rate V18 18 1. ...
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Electrical parameters 6.3.4 Supply current characteristics The current consumption is measured as described in on page 30. Subject to general operating conditions for V Maximum power consumption For the measurements in conditions: ● All I/O pins are configured in output ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 14. Maximum power consumption in STOP and STANDBY modes Symbol Parameter LP_PARAM bits: ALL OFF Single supply scheme see LP_PARAM bits: ALL OFF Supply Dual supply scheme see current in LP_PARAM bits: ALL OFF STOP ...
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Electrical parameters Figure 16. Power consumption in STOP mode in Single supply scheme (3.3 V range) 300 250 TYP (3.3V) MAX (3.6V) 200 150 100 Temp (°C) Figure 18. Power consumption in STANDBY mode ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Typical power consumption The following measurement conditions apply to In RUN mode: ● Program is executed from Flash (except if especially mentioned). The program consists of an infinite loop. When f ● A standard 4 MHz ...
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Electrical parameters Subject to general operating conditions for V Table 15. Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes Symbol Para meter Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: f ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 16. Dual supply supply typical power consumption in Run, WFI, Slow and Slow-WFI modes To calculate the power consumption in Dual supply mode, refer to the values given in consider that this consumption is split ...
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Electrical parameters Supply and clock manager power consumption Table 18. Supply and clock manager Symbol Parameter Supply current of resonator oscillator I in STOP or WFI mode (LP_PARAM DD(OSC4M) bit: OSC4M ON) FLASH static current consumption in I STOP or ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx On-Chip peripheral power consumption Conditions: – DD_IO – 25° – Clocked by OSC4M with PLL multiplication =32 MHz PCLK . Table 19. On-Chip peripherals Symbol I TIM Timer ...
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Electrical parameters 6.3.5 Clock and timing characteristics XT1 external clock source Subject to general operating conditions for V Table 20. XT1 external clock source Symbol External clock source f XT1 frequency XT1 input pin high level V XT1H voltage XT1 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx XRTC1 external clock source Subject to general operating conditions for V Table 21. XRTC1 external clock source Symbol External clock source f XRTC1 frequency XRTC1 input pin high V XRTC1H level voltage XRTC1 input pin low ...
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Electrical parameters 4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2) The STR750 system clock or the input of the PLL can be supplied by a OSC4M which MHz clock generated from a 4 MHz or 8 MHz ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external ...
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Electrical parameters difference between N+1 consecutive clock rising edges and T difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx PLL characteristics Subject to general operating conditions for V Table 24. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT f VCO frequency range VCO t ...
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Electrical parameters 6.3.6 Memory characteristics Flash memory Subject to general operating conditions for V otherwise specified. Table 26. Flash memory characteristics Symbol t Word Program PW t Double Word Program PDW t Bank 0 Program (256K) PB0 t Bank 1 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.3.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electro magnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product ...
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Electrical parameters Electro magnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...
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... Static latch-up class DLU Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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Electrical parameters 6.3.8 I/O port pin characteristics General characteristics Subject to general operating conditions for V Table 32. General characteristics Symbol V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys hysteresis I ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 25. Connecting unused I/O pins Output driving current The GP I/Os have different drive capabilities: ● O2 outputs can sink or source up to +/-2 mA. ● O4 outputs can sink or source up to ...
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Electrical parameters Table 33. Output driving current I/O Symbol Type Output low level voltage for a standard (1) V I/O pin when 8 pins are sunk at same OL time O2 Output high level voltage for an I/O pin (2) ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Output speed Subject to general operating conditions for V Table 34. Output speed I/O Symbol Type f max(IO)out t f(IO)out O2 t r(IO)out f max(IO)out t f(IO)out O4 t r(IO)out f max(IO)out t f(IO)out O8 t ...
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Electrical parameters NRSTIN and NRSTOUT pins NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as R NRSTOUT Pin Output Driver is equivalent to the O2 type driver except ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 27. Recommended NRSTIN pin protection EXTERNAL RESET CIRCUIT 1. The user must ensure that the level on the NRSTIN pin can go below the V NRSTIN and NRSTOUT pins on page V DD_IO R PU ...
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Electrical parameters 6.3.9 TB and TIM timer characteristics Subject to general operating conditions for V specified. Refer to Section 6.3.8: I/O port pin characteristics on page 54 input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 37. PWM Timer (PWM) Symbol t PWM resolution time res(PWM) Res PWM resolution PWM PWM/DAC output step ( voltage Timer clock period t when internal clock is COUNTER selected Maximum Possible t MAX_COUNT ...
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Electrical parameters 6.3.10 Communication interface characteristics SSP synchronous serial peripheral in master mode (SPI or TI mode) General operating conditions: V Table 38. SSP master mode characteristics Symbol f SPI clock frequency SCK t SPI clock rise time r(SCK) t ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 28. SPI configuration - master mode, single transfer NSS OUTPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO DONT CARE INPUT t NSSLQV MOSI OUTPUT Figure 29. SPI configuration - master mode, continuous transfer, ...
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Electrical parameters Figure 31. TI configuration - master mode, single transfer NSS OUTPUT SCK OUTPUT MISO DONT CARE INPUT MOSI OUTPUT Figure 32. TI configuration - master mode, continuous transfer NSS OUTPUT trigger sample SCK OUTPUT MOSI ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx SSP synchronous serial peripheral in slave mode (SPI or TI mode) Subject to general operating conditions with C Table 39. SSP slave mode characteristics Symbol f SPI clock frequency SCK NSS input setup time w.r.t t ...
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Electrical parameters Figure 34. SPI configuration - slave mode with CPHA=0, continuous transfer 1.5*t NSS INPUT CPOL=0 CPOL=1 MISO OUTPUT DONT CARE MOSI INPUT Figure 35. SPI configuration, slave mode with CPHA=1, single transfer NSS INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 37. TI configuration - slave mode, single transfer NSS INPUT t SCK INPUT MOSI DONT CARE INPUT MISO z OUTPUT Figure 38. TI configuration - slave mode, continuous transfer NSS OUTPUT trigger sample SCK OUTPUT ...
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Electrical parameters SMI - serial memory interface Subject to general operating conditions with C Table 40. SMI characteristics Symbol f SMI clock frequency SMI_CK t SMI clock rise time r(SMI_CK) t SMI clock fall time f(SMI_CK) t Data output valid ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx not possible to power off the STR7x while some another I powered on: otherwise, the STR7x will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function ...
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Electrical parameters 6.3.11 USB characteristics The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time Symbol t STARTUP Table 43. USB characteristics Symbol V Differential Input Sensitivity DI Differential Common Mode V CM Single Ended Receiver V ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 44. USB: Full speed electrical characteristics Symbol t Rise/ Fall Time matching rfm V Output signal Crossover Voltage CRS 1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer ...
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Electrical parameters 6.3.12 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 45. 10-bit ADC characteristics Symbol f ADC clock frequency ADC V Conversion voltage range AIN R External input impedance AIN External capacitor on analog C ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx ADC accuracy vs. negative injection current Injecting negative current on specific pins listed in input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed recommended to ...
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Electrical parameters General PCB design guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. ● Use separate digital ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 47. ADC accuracy ADC accuracy with f This assumes that the ADC is calibrated Symbol |E | Total unadjusted error Offset error O E Gain Error Differential linearity error ...
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Package characteristics 7 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 46. 100-pin low profile flat package (14x14 Figure 47. 64-ball low profile fine pitch ball grid array package Dim. Min 0. 1.35 1.40 1.45 0.0531 0.0551 0.0571 ...
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Package characteristics Figure 48. 100-ball low profile fine pitch ball grid array package Figure 49. Recommended PCB design rules (0.80/0.75mm pitch BGA) 78/84 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Dim. Min A A1 0.270 0.45 D 9.85 D1 ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 7.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: is the maximum Ambient Temperature in °C, – T Amax ...
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Package characteristics 7.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code Table 49: Order codes on page The following example shows how to calculate the temperature range needed for a ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 8 Order codes Table 49. Order codes Order code STR750FV0T6 STR750FV1T6 STR750FV2T6 STR750FV0H6 STR750FV1H6 STR750FV2H6 STR751FR0T6 STR751FR1T6 STR751FR2T6 STR751FR0H6 STR751FR1H6 STR751FR2H6 STR752FR0T6 STR752FR1T6 STR752FR2T6 STR752FR0H6 STR752FR1H6 STR752FR2H6 STR752FR0T7 STR752FR1T7 STR752FR2T7 STR752FR0H7 STR752FR1H7 STR752FR2H7 STR755FR0T6 STR755FR1T6 STR755FR2T6 STR755FR0H6 STR755FR1H6 STR755FR2H6 Flash Prog ...
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Order codes Table 49. Order codes (continued) Order code STR755FV0T6 STR755FV1T6 STR755FV2T6 STR755FV0H6 STR755FV1H6 STR755FV2H6 82/84 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Flash Prog. Memory Package (Bank 0) Kbytes 64 128 LQFP100 14x14 256 64 128 LFBGA100 10x10 256 Nominal CAN USB ...
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 9 Revision history Table 50. Document revision history Date Revision 25-Sep-2006 30-Oct-2006 04-Jul-2007 23-Oct-2007 17-Feb-2009 Description of Changes 1 Initial release 2 Added power consumption data for 5V operation in Changed datasheet title from STR750F to ...
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