ST6225C STMicroelectronics, ST6225C Datasheet

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... MCUs with A/D converter, two timers, oscillator safeguard & safe reset (See Development Tools ■ – Full hardware/software development package ST6215C 2K 3. 8MHz Max -40°C to +125°C PDIP28 / SO28 / SSOP28 Rev 4 ST6215C ST6225C PDIP28 S028 SS0P28 CDIP28W Section 12.5 for Ordering Information) ST6225C 4K 64 1/105 1 ...

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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... ST6215C ST6225C 1 INTRODUCTION The ST6215C, 25C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrol- lers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is sur- rounded by a number of on-chip peripherals. ...

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... Must be held at Vss for normal operation 12.5V level is applied to the pin during the reset phase, the device enters EPROM programming mode. Top priority non maskable interrupt (active low) Pin B7 (IPU) Pin B6 (IPU) ST6215C ST6225C V SS PA0/20mA Sink PA1/20mA Sink PA2/20mA Sink ...

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... ST6215C ST6225C Pin n° Pin Name 14 PB5/Ain I/O 15 PB4/Ain I/O 16 PB3/Ain I/O 17 PB2/Ain I/O 18 PB1/Ain I/O 19 PB0/Ain I/O 20 PA7/Ain I/O 21 PA6/Ain I/O 22 PA5/Ain I/O 23 PA4/Ain I/O 24 PA3/ 20mA Sink I/O 25 PA2/ 20mA Sink I/O 26 PA1/ 20mA Sink I/O 27 PA0/ 20mA Sink I Legend / Abbreviations for Table I = input output supply, IPU = input pull-up The input with pull-up configuration (reset state) is valid as long as the user software does not change it. ...

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... Briefly, Program space contains user program code in OTP and user vectors; Data space con- tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. 10) ST6215C ST6225C DATA SPACE 000h RESERVED 03Fh 040h ...

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... ST6215C ST6225C MEMORY MAP (Cont’d) Figure 4. Program Memory Map ST6215C 0000h NOT IMPLEMENTED 07FFh 0800h RESERVED 087Fh 0880h USER PROGRAM MEMORY 1824 BYTES 0F9Fh 0FA0h RESERVED 0FEFh 0FF0h INTERRUPT VECTORS 0FF7h 0FF8h RESERVED 0FFBh 0FFCh NMI VECTOR 0FFDh 0FFEh USER RESET VECTOR ...

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... Data ROM Win- dow register (DRWR register). 3.1.5 Stack Space Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. ST6215C ST6225C 11/105 1 ...

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... ST6215C ST6225C MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block Label 080h CPU X,Y,V,W to 083h 0C0h DRA 0C1h I/O Ports DRB 0C2h DRC 0C3h 0C4h DDRA 0C5h I/O Ports DDRB 0C6h DDRC 0C7h 0C8h CPU IOR 0C9h ROM DRWR 0CAh 0CBh ...

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... Caution: This register is undefined on reset write-only, therefore do not read it nor access it us- 040h ing Read-Modify-Write instructions (SET, RES, DATA ROM INC and DEC). WINDOW 07Fh 0FFh ST6215C ST6225C DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0 0 13/105 1 ...

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... ST6215C ST6225C MEMORY MAP (Cont’d) 3.1.6.2 Data ROM Window memory addressing In cases where some data (look-up tables for ex- ample) are stored in program memory, reading these data requires the use of the Data ROM win- dow mechanism this: 1. The DRWR register has to be loaded with the 64-byte block number where the data are located (in program memory) ...

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... Board. Table 3. ST6215C Program Memory Map Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh NMI Interrupt Vector 0FFEh-0FFFh Table 4. ST6225C Program Memory Map Device Address 0000h-007Fh 0080h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh NMI Interrupt Vector 0FFEh-0FFFh Note: OTP/EPROM devices can be programmed ...

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... ST6215C ST6225C 3.3 OPTION BYTES Each device is available for production in user pro- grammable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while ROM factory coded parts contain the code sup- plied by the customer. This implies that OTP de- ...

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... ROM location may be an opcode, an operand, or the address of an operand. 0 ACCUMULATOR 0 X INDEX REGISTER 0 Y INDEX REGISTER 0 V SHORT INDIRECT REGISTER 0 W SHORT INDIRECT REGISTER 0 PROGRAM COUNTER ST6215C ST6225C SIX LEVEL STACK CN NORMAL FLAGS CI INTERRUPT FLAGS CNMI ZNMI NMI FLAGS x = Undefined value 17/105 ...

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... ST6215C ST6225C CPU REGISTERS (Cont’d) The 12-bit length allows the direct addressing of 4096 bytes in Program Space. However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program ROM Page register. The PC value is incremented after reading the ad- dress of the current instruction ...

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... Program Counter). An instruction may require two, four, or five CPU cycles for execution. OSCILLATOR SAFEGUARD (OSG) OSG filtering 0 1 LFAO OSCOFF BIT (ADCR REGISTER) ST6215C ST6225C illustrates various possible oscillator con the lowest cost solution using only NET INT Figure 9. SPI : 13 CORE ...

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... ST6215C ST6225C CLOCK SYSTEM (Cont’d) 5.1.1 Main Oscillator The oscillator configuration is specified by select- ing the appropriate option in the option bytes (refer to the Option Bytes section of this document). When the CRYSTAL/RESONATOR option is se- lected, it must be used with a quartz crystal, a ce- ramic resonator or an external signal provided on the OSCin pin ...

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... Figure depending on both V cise timing measurements not recommended to use the OSG OSC> OSG INTERNAL CLOCK DRIVEN BY LFAO ST6215C ST6225C , is limited to INT Management of Supply : the maximum authorised frequen- OSG (see Electrical OSG and temperature. For pre- ...

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... ST6215C ST6225C CLOCK SYSTEM (Cont’d) 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a backup oscillator in case of main oscillator fail- ure ...

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... MCU starts run- ning and sinks current on the supply (hysteresis). Figure 12. Low Voltage Detector Reset IT+ V IT- RESET ST6215C ST6225C The LVD Reset circuitry generates a reset when V is below: DD – V when V is rising DD IT+ – V ...

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... ST6215C ST6225C 5.3 RESET 5.3.1 Introduction The MCU can be reset in three ways: A low pulse input on the RESET pin ■ Internal Watchdog reset ■ Internal Low Voltage Detector (LVD) reset ■ 5.3.2 RESET Sequence The basic RESET sequence consists of 3 main phases: Internal (watchdog or LVD) or external Reset ■ ...

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... A simple external RESET circuitry is shown in ure 15. For more details, please refer to the appli- cation note AN669. f INT ESD ST6215C ST6225C Fig- INTERNAL RESET WATCHDOG RESET LVD RESET 25/105 1 ...

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... ST6215C ST6225C RESET (Cont’d) 5.3.4 Watchdog Reset The MCU provides a Watchdog timer function in order to be able to recover from software hang- ups. If the Watchdog register is not refreshed be- fore an end-of-count condition is reached, a Watchdog reset is generated. After a Watchdog reset, the MCU restarts in the same way Reset was generated by the RE- SET pin ...

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... Interrupts are triggered by events either on exter- nal pins, or from the on-chip peripherals. Several events can be ORed on the same interrupt vector. Interrupt On-chip peripherals have flag registers to deter- mine which event triggered the interrupt. ST6215C ST6225C 27/105 1 ...

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... ST6215C ST6225C Figure 17. Interrupts Block Diagram NMI I/O PORT REGISTER PA0..PA7 “INPUT WITH INTERRUPT” CONFIGURATION I/O PORT REGISTER PB0..PB7 “INPUT WITH INTERRUPT” PC4..PC7 CONFIGURATION TIMER (TSCR REGISTER) A/D CONVERTER (ADCR REGISTER) 28/105 1 LATCH CLEARED BY H/W AT START OF VECTOR #0 ROUTINE ...

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... The corresponding enable bit is set in the periph- eral control register. Peripheral interrupts are linked to vectors #3 and #4. Interrupt requests are flagged by a bit in their corresponding control register. This means that a request cannot be lost, because the flag bit must be cleared by user software. ST6215C ST6225C 29/105 1 ...

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... ST6215C ST6225C 6.5 EXTERNAL INTERRUPTS (I/O Ports) External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the GEN bit is set. These interrupts allow the processor to exit from STOP mode. The external interrupt polarity is selected through the IOR register. ...

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... Program Counter is loaded with the in- terrupt vector and when the program has jump to the interrupt subroutine and is ready to execute the code. It depends on when the interrupt occurs while the core is processing an instruction. ST6215C ST6225C Figure 18. Interrupt Processing Flow Chart INSTRUCTION FETCH INSTRUCTION ...

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... ST6215C ST6225C 6.7 REGISTER DESCRIPTION INTERRUPT OPTION REGISTER (IOR) Address: 0C8h — Write Only Reset status: 00h 7 - LES ESB GEN - Caution: This register is write-only and cannot be accessed by single-bit operations (SET, RES, DEC,...). Bit 7 =Reserved, must be cleared. Bit 6 = LES Level/Edge Selection bit. 0: Falling edge sensitive mode is selected for inter- rupt vector #1 Table 7 ...

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... From Run mode, the different power saving modes may be selected by calling the specific ST6 software instruction or for the LFAO by setting the relevant register bit. For more information on the LFAO, please refer to the Clock chapter. ST6215C ST6225C Figure 19. Power Saving Mode Transitions High RUN LFAO ...

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... ST6215C ST6225C 7.2 WAIT MODE The MCU goes into WAIT mode as soon as the WAIT instruction is executed. This has the follow- ing effects: – Program execution is stopped, the microcontrol- ler software can be considered as being in a “fro- zen” state. – RAM contents and peripheral registers are pre- served as long as the power supply voltage is higher than the RAM retention voltage ...

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... NMI pin. In this case, the STOP instruction will be exe- cuted and the Watchdog will be frozen. Figure 21. STOP Mode Timing Overview RUN STOP INSTRUCTION ) is INT ST6215C ST6225C 21). 2048 CLOCK CYCLE STOP RUN DELAY RESET ...

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... ST6215C ST6225C STOP MODE (Cont’d) Figure 22. STOP Mode Flowchart EXCTNL 1) VALUE 0 OSCILLATOR Clock to PERIPHERALS Clock to CPU N RESET N INTERRUPT Y Notes: 1. EXCTNL is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from STOP mode (such as external interrupt). Refer to the Interrupt Mapping table for more details ...

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... Normal Interrupt Mode. If the MCU was in inter- rupt mode before the STOP or WAIT instruction was executed, it exits from STOP or WAIT mode ST6215C ST6225C as soon as an interrupt occurs. Nevertheless, two cases must be considered: – If the interrupt is a normal one, the interrupt rou- ...

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... ST6215C ST6225C 8 I/O PORTS 8.1 INTRODUCTION Each I/O port contains pins. Each pin can be programmed independently as digital input (with or without pull-up and interrupt generation), digital output (open drain, push-pull) or analog in- put (when available). The I/O pins can be used in either standard or al- ternate function mode. ...

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... With pull-up, no interrupt Input No pull-up, no interrupt Input With pull-up and with interrupt Input Analog input (when available) Output Open-drain output (20mA sink when available) Output Push-pull output (20mA sink when available) ST6215C ST6225C Pxx I/O Pin N-BUFFER CLAMPING DIODES ...

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... ST6215C ST6225C I/O PORTS (Cont’d) 8.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) DO NOT USE READ-MODIFY-WRITE INSTRUC- TIONS (SET, RES, INC and DEC) ON PORT DATA REGISTERS IF ANY PIN OF THE PORT IS CONFIGURED IN INPUT MODE. These instructions make an implicit read and write back of the entire register ...

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... ORx DRx 1 1 0/1 Note 1. Provided the correct configuration has been selected (see AVAILABLE ( ST6215C ST6225C SCHEMATIC Data in Interrupt ADC P-buffer disconnected Data out Data out Table 8). Data in Interrupt Data in Interrupt 41/105 ...

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... ST6215C ST6225C I/O PORTS (Cont’d) 8.5 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register DRx with Addresses 0C0h, 0C1h and 0C2h- Read/Write Reset Value: 0000 0000 (00h) 7 DR7 DR6 DR5 DR4 DR3 Bits 7:0 = DR[7:0] Data register bits. Reading the DR register returns either the DR reg- ...

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... Software reset ■ Reset (if watchdog activated) when the SR bit ■ reaches zero Hardware or software watchdog activation ■ selectable by option bit (Refer to the option bytes section 7-BIT DOWNCOUNTER CLOCK DIVIDER ÷ 256 ST6215C ST6225C RESET SR C bit 0 43/105 1 ...

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... ST6215C ST6225C WATCHDOG TIMER (Cont’d) 9.1.3 Functional Description The watchdog activation is selected through an option in the option bytes: – HARDWARE Watchdog option After reset, the watchdog is permanently active, the C bit in the WDGR is forced high and the user can not change it. However, this bit can be read equally – ...

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... STOP mode. When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity. 9.1.6 Interrupts None. ST6215C ST6225C Note: This note applies only when the watchdog is used as a standard timer recommended to read the counter twice may sometimes return ...

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... ST6215C ST6225C WATCHDOG TIMER (Cont’d) 9.1.7 Register Description WATCHDOG REGISTER (WDGR) Address: 0D8h - Read/Write Reset Value: 1111 1110 (FEh Bits 7:2 = T[5:0] Downcounter bits Caution: These bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB ...

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... The timer can be used in WAIT and STOP modes to wake up the MCU. 7 8-BIT DOWN COUNTER TCR7 TCR6 TCR5 TCR4 LATCH 7 TMZ ETI TOUT DOUT f PRESCALER PSCR REGISTER /64 /32 / ST6215C ST6225C 0 TCR3 TCR2 TCR1 TCR0 0 TSCR PSI PS2 PS1 PS0 REGISTER COUNTER 47/105 1 ...

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... ST6215C ST6225C 8-BIT TIMER (Cont’d) 9.2.3 Counter/Prescaler Description Prescaler The prescaler input can be the internal frequency f divided external clock applied to INT the TIMER pin. The prescaler decrements on the rising edge, depending on the division factor pro- grammed by the PS[2:0] bits in the TSCR register. ...

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... I/O Ports section. Figure 28. f TIMER Figure 29. Gated Mode Operation Application COUNTER VALUE xx1 source measurement xx2 Output signal generation TIMER PIN 1 29. TIMER CLOCK ST6215C ST6225C Clock in Gated Mode TIMER f /12 INT f PRESCALER f EXT VALUE 1 VALUE 2 PULSE LENGTH 49/105 1 ...

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... ST6215C ST6225C 8-BIT TIMER (Cont’d) 9.2.4.2 Event Counter Mode (TOUT = “0”, DOUT = “0”) In this mode, the TIMER pin is the input clock of the Timer prescaler which is decremented on eve- ry rising edge of the input clock (allowing event count). See Figure 30 and Figure This mode is selected by clearing the TOUT bit in the TSCR register (i ...

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... Description No effect on timer. WAIT Timer interrupt events cause the device to exit from WAIT mode. Timer registers are frozen except in Event STOP Counter mode (with external clock on TIM- ER pin). ST6215C ST6225C 9.2.6 Interrupts Event Enable Interrupt Event Flag Bit Timer Zero TMZ ETI ...

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... ST6215C ST6225C 8-BIT TIMER (Cont’d) 9.2.7 Register Description PRESCALER COUNTER REGISTER (PSCR) Address: 0D2h - Read/Write Reset Value: 0111 1111 (7Fh) 7 PSCR PSCR PSCR PSCR PSCR Bit 7 = PSCR7: Not used, always read as “0”. Bits 6:0 = PSCR[6:0] Prescaler LSB. TIMER COUNTER REGISTER (TCR) ...

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... Typical conversion time 70 µs (with an 8 MHz ■ crystal) The block diagram is shown in f INT DIV OSC CR3 OFF CR1 I/O PORT MUX DDRx ADR ORx DRx ADR7 ADR6 ADR5 ADR4 ST6215C ST6225C Figure f ADC AD ADCR CR0 ANALOG TO DIGITAL CONVERTER ADR3 ADR2 ADR1 34. ADR0 53/105 1 ...

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... ST6215C ST6225C A/D CONVERTER (Cont’d) 9.3.3 Functional Description 9.3.3.1 Analog Power Supply The high and low level reference voltage pins are internally connected to the V DD Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. ...

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... R conversion accuracy). Figure 35. Leakage from Digital Inputs ). The user must SS and V pins DD SS pin AIN ST6215C ST6225C voltage. The negative effect of this var- DD < V INJ SS 35. To avoid this: (to reduce the IN J ADC Digital Input PBy/AINy R INJ ...

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... ST6215C ST6225C A/D CONVERTER (Cont’d) 9.3.5 Low Power Modes Mode Description No effect on A/D Converter. ADC interrupts WAIT cause the device to exit from Wait mode. STOP A/D Converter disabled. Note: The A/D converter may be disabled by clear- ing the PDS bit. This feature allows reduced power consumption when no conversion is needed. ...

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... The instructions (JP, CALL) which use ex- ST6215C ST6225C tended addressing mode are able to branch to any address in the 4 Kbyte Program space. Extended addressing mode instructions are two bytes long ...

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... ST6215C ST6225C 10.3 INSTRUCTION SET The ST6 offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...

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... Immediate data (stored in ROM memory) * Not Affected rr Data space register ST6215C ST6225C Flags Z C Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ ...

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... ST6215C ST6225C INSTRUCTION SET (Cont’d) Conditional Branch. Branch instructions perform a branch in the program when the selected condi- tion is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in Data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...

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... JRNC 5 JRS 2 JRZ 4 e b7,rr,ee e pcr pcr 1 # Indicates Illegal Instructions e 5-bit Displacement b 3-bit Address rr 1-byte Data space address nn 1-byte immediate data abc 12-bit address ee 8-bit displacement ST6215C ST6225C 0101 0110 0111 2 JRC a,(x) 1 prc 1 ind INC 2 JRC 4 LDI ...

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... ST6215C ST6225C Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ abc 0010 1 pcr 2 ext 1 2 JRNZ abc 0011 1 pcr 2 ...

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... The loading conditions used for pin parameter measurement is shown in Figure Figure 36. Pin Loading Conditions =25°C A 11.1.5 Pin Input Voltage The input voltage measurement on a pin of the de- vice is described in Figure 37. Pin Input Voltage ≤6.0V DD =3.3V (for the 36. ST6215C ST6225C ST6 PIN C L Figure 37. ST6 PIN V IN 63/105 1 ...

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... ST6215C ST6225C 11.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 11.2.1 Voltage Characteristics Symbol Supply voltage DD SS ...

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... Suffix DD f =4MHz, 1 & 6 Suffix OSC f =4MHz, 3 Suffix OSC f =8MHz, 1 & 6 Suffix OSC f =8MHz, 3 Suffix OSC 1 Suffix Version 6 Suffix Version 3 Suffix Version DD 1 & 6 suffix version 3 suffix version 3.6 4 4.5 5 ST6215C ST6225C Min Max 3 3.0 6.0 3.0 6.0 3.6 6.0 4.5 6 ...

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... ST6215C ST6225C OPERATING CONDITIONS (Cont’d) 11.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+ (V rise) DD Reset generation threshold V IT- (V fall LVD voltage threshold hysteresis hys rise time rate POR ...

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... OSC 43) f =4MHz OSC f =8MHz OSC ≤6.0V range) and V =5V (4.5V≤ Figure 43. Typical I CPU (V = 5V) DD IDD [mA] 3.5 3 2.5 2 1 ST6215C ST6225C 1) Typ Max 0.5 1.3 1.6 2.2 3.3 0.3 0.6 0.9 1.0 1.8 ≤3.6V range). =3.3V (3V≤ max. and f max. OSC in RUN vs. Temperature DD 8MHz 4MHz 2MHz - T[°C] ...

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... ST6215C ST6225C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 11.4.2 WAIT Modes Symbol Parameter Supply current in WAIT mode Option bytes not programmed (see Figure 44) Supply current in WAIT mode Option bytes programmed to 00H (see Figure 45) Supply current in WAIT mode (see Figure 46 Supply current in WAIT mode ...

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... Temperature for OTP devices with option bytes CPU IDD [µ -20 ST6215C ST6225C 8MHz 1MHz 4MHz 32KHz 2MHz 25 95 125 T[°C] 8MHz 1MHz 4MHz 32KHz 2MHz 25 95 T[°C] 69/105 1 ...

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... ST6215C ST6225C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 46. Typical I in WAIT IDD [µA] 600 8MHz 1M 4MHz 32KHz 500 2MHz 400 300 200 100 VDD [V] 70/105 1 and Temperature for ROM devices CPU IDD [µA] 450 400 350 300 250 200 ...

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... VDD [V] Conditions OTP devices 2) 48) ROM devices =25°C. A Figure 48. Typical I for ROM devices IDD [nA] 1500 1000 500 ST6215C ST6225C 1) Typ Max max. and f max. DD CPU in STOP vs Temperature DD Ta=-40°C Ta=95°C Ta=25°C Ta=125°C ...

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... ST6215C ST6225C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 11.4.4 Supply and Clock System The previous current consumption specified for the ST6 functional operating modes over tempera- ture range does not take into account the clock Symbol Parameter Supply current of RC oscillator I DD(CK) Supply current of resonator oscillator ...

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... T DD OSC A Conditions f =8 MHz CPU MHz CPU Conditions See Figure 49 ≤V ≤ 90% 10% OSC OUT OSC IN ST6215C ST6225C . 1) Min Typ Max 3.25 6.5 8.125 6 11 9.75 17.875 Min Typ Max 0.7xV 0.3xV SS ± the number of t ...

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... ST6215C ST6225C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 11.5.3 Crystal and Ceramic Resonator Oscillators The ST6 internal clock can be supplied with sever- al different Crystal/Ceramic resonator oscillators. Only parallel resonant crystals can be used. All the information given in this paragraph are based on Symbol Parameter ...

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... NET R =100 kΩ NET R =220 kΩ NET R =470 kΩ NET 1) R =22 kΩ NET R =47 kΩ NET R =100 kΩ NET R =220 kΩ NET R =470 kΩ NET 2) see Figure 52 & f OSC C ~9pF DISCHARGE EX ST6215C ST6225C R NET Min Typ Max 7.2 8.6 10 5.1 5.7 6.5 3.2 3.4 3.8 1.8 1.9 0.9 0.95 1.1 3.7 4.3 4.9 2.8 3 3.3 1.8 1.9 1 1.1 1.2 0.5 0.55 0.6 Figure 53 22 ...

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... ST6215C ST6225C CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 52. Typical RC Oscillator frequency vs Rnet=22KOhm fosc [MHz] Rnet=47KOhm 12 Rnet=100KOhm 10 Rnet=220KOhm 8 Rnet=470KOhm VDD [V] 11.5.5 Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) Symbol Parameter Low Frequency Auxiliary Oscillator f 1) LFAO ...

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... The data retention time increases when the and T unless otherwise specified. DD OSC A Conditions Conditions 3) T =+55° Temperature [°C] decreases, see Figure 55. A ST6215C ST6225C Min Typ Max Unit 0.7 Min Typ Max Unit 10 years 100 110 120 V 77/105 1 ...

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... ST6215C ST6225C 11.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 11.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ...

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... R (machine resistance), in series with S2, en- sures a slow discharge of the ST6. Conditions =+25° =+25° HIGH VOLTAGE ST6 PULSE S2 GENERATOR ST6215C ST6225C through R (body resistance the ST6 occurs Maximum value Unit 2000 V 200 S1 ST6 =200pF S2 ...

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... ST6215C ST6225C EMC CHARACTERISTICS (Cont’d) 11.7.2.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required ■ parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample ...

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... To protect the input structure the following ele- ments are added: – A resistor in series with the pad (1) – A diode to V – A protection device between V for standard SS (3a) (4) OUT (3b) DD (3a) (4) OUT (3b) ST6215C ST6225C (3a) and a diode from and (2a) and a diode from and (2a) (1) IN ...

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... ST6215C ST6225C 11.8 I/O PORT PIN CHARACTERISTICS 11.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input leakage current L R Weak pull-up equivalent resistor PU C I/O input pin capacitance ...

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... VSS . True open drain I/O pins does not have V VDD = 5V (standard) Figure 64. Typical V Vol [V] at Vdd=5V 1 Ta=-40°C 0.8 Ta=25°C 0.6 0.4 0 ST6215C ST6225C unless otherwise specified. Min Max ≤ 125°C 0.1 A ≤ 125°C 0.8 A ≤ 85°C 0.8 A ≤ 85°C 1.2 A ≤ 125°C ...

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... ST6215C ST6225C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 65. Typical Voh [V] at Vdd=5V 4.5 4 3.5 Figure 66. Typical Vol [mV] at Iio=2mA Ta=-40°C 350 Ta=25°C 300 250 200 150 3 4 VDD [V] Figure 67. Typical Vol [V] at Iio=8mA 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0 VDD [V] 84/105 Ta=-40° ...

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... I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 68. Typical Voh [V] at Iio=-2mA VDD [V] Voh [V] at Iio=-5mA Ta=-40°C Ta=95°C 3 Ta=25°C Ta=125° ST6215C ST6225C Ta=-40°C Ta=95°C Ta=25°C Ta=125° VDD [V] 85/105 1 ...

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... ST6215C ST6225C 11.9 CONTROL PIN CHARACTERISTICS 11.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys R Weak pull-up equivalent resistor ON R ESD resistor protection ESD t Generated reset pulse duration ...

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... V = =3.3V DD =25°C and V A with Ta=-40°C Ta=25° VDD [V] ST6215C ST6225C f INT STOP MODE WATCHDOG RESET LVD RESET unless otherwise specified. 1) Min Typ Max 0.3xV 0.7xV DD 200 400 40 100 350 80 200 700 =5V. DD Ta=95°C Ta=125° ...

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... ST6215C ST6225C CONTROL PIN CHARACTERISTICS (Cont’d) 11.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 11.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 11.10.2 8-Bit Timer Symbol Parameter f Timer external clock frequency EXT t Pulse width at TIMER pin ...

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... Note: ADC not present on some devices. See device summary on page and T DD OSC Conditions 2) f =8MHz OSC f =4MHz OSC f =8MHz OSC =25°C and r≈150Ω AINx 10pF ST6215C ST6225C unless otherwise specified Min Typ Max 1.2 f OSC 140 2 3.25 6.5 1.0 2 =5V. ...

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... ST6215C ST6225C 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter |E | Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L Notes: 1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs ...

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... Figure 74. 28-Pin Plastic Dual In-Line Package, 600-mil Width Figure 75. 28-Pin Plastic Small Outline Package, 300-mil Width 45× ST6215C ST6225C mm inches Dim. Min Typ Max Min Typ A 6.35 A1 0.38 0.015 A2 3.18 4.95 0.125 B 0.36 0.56 0.014 B1 0.76 1.78 0.030 C 0.20 0.38 0.008 D 35 ...

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... ST6215C ST6225C PACKAGE MECHANICAL DATA (Cont’d) Figure 76. 28-Pin Ceramic Side-Brazed Dual In-Line Package Figure 77. 28-Pin Plastic Shrink Small Outline Package 92/105 1 CDIP28W inches Dim. Min Typ Max Min Typ Max A 4.17 A1 0.76 0.030 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 0 ...

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... The power dissipation is obtained from the formula P and P is the port power dissipation determined by the user. PORT 2. The average chip-junction temperature can be obtained from the formula T Ratings where P D INT PORT J ST6215C ST6225C Value Unit 55 °C/W 75 110 500 mW 150 °C is the chip internal power (I INT RthJA ...

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... ST6215C ST6225C 12.3 ECOPACK INFORMATION In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK tions, grade definitions and product status are available at: www.st.com. ECOPACK trademark. 94/105 1 ® specifica- ® ...

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... EMU PROBE (sales type: ST626X-P/SSOP28) Programming Logical Systems Adapter Adaptor / Socket Reference 228-60-23 Adaptor / Socket Reference OTS-28-1.27-04 IC51-0282-334-1 PA28SO1-08-6 Adaptor / Socket Reference OTS-28-0.65-01 PA28SS-OT-6 ST6215C ST6225C Same Socket Type Footprint X Textool Same Socket Type Footprint Open Top Clamshell X SMD to DIP X ...

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... ST6215C ST6225C 12.5 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics Figure 78. ST6 Factory Coded Device Types ST62T25CB6/CCC 96/105 1 and also details the ST6 factory coded device type. ROM code Temperature code: 1: Standard 0 to +70 °C 3: Automotive -40 to +125 °C 6: Industrial -40 to +85 ° ...

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... FASTROM Version The ST62P15C/P25C are the Factory Advanced Service Technique ROM (FASTROM) versions of ST62T15C,T25C OTP devices. ST6215C ST6225C They offer the same functionality as OTP devices, but they do not have to be programmed by the customer. The customer code must be sent to STMicroelectronics in the same way as for ROM devices ...

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... ST6215C ST6225C TRANSFER OF CUSTOMER CODE (Cont’d) 12.6.2 ROM Version The ST6215C/25C are mask programmed ROM version of ST62T15C,T25C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 79. Programming Circuit 5V 4.7µ ...

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... ST6215C (2 KB ST6225C (4 KB ST62P15C (2 KB) ...

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... ST6215C ST6225C 13 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST6 micro- controller family. Full details of tools available for the ST6 from third party manufacturers can be ob- Table 25. Dedicated Third Parties Development Tools 1) Third Party ST-REALIZER II: Graphical Schematic ...

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... ST6 HDS2 Emulator tion features including trace/ logic analyzer ST6 EPROM No Programmer Board Table 27. Dedicated STMicroelectronics Development Tools Supported Products ST6215C and ST6225C Programming Capability Yes (DIP packages only) No Yes (All packages except SSOP) ST6 Starter Kit ST6 HDS2 Emulator Complete: ...

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... ST6215C ST6225C 14 ST6 APPLICATION NOTES IDENTIFICATION MOTOR CONTROL AN392 MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS AN414 CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU AN416 SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC AN422 IMPROVES UNIVERSAL MOTOR DRIVE AN863 IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR ...

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... MAKING IT EASY WITH MICROCONTROLLERS AN898 EMC GENERAL INFORMATION AN899 SOLDERING RECOMMENDATIONS AND PACKAGING INFORMATION AN900 INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY AN901 EMC GUIDE-LINES FOR MICROCONTROLLER - BASED APPLICATIONS AN902 QUALITY AND RELIABILITY INFORMATION AN912 A SIMPLE GUIDE TO DEVELOPMENT TOOLS AN1181 ELECTROSTATIC DISHARGE SENSITIVITY MEASUREMENT ST6215C ST6225C DESCRIPTION 103/105 1 ...

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... ST6215C ST6225C 15 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Removed references to 32768 clock cycle delay in 3.3 Changed note 2 in Section 11.6.2 on page mability. Updated device summary on page 1 4 Replaced soldering information by ECOPACK Updated disclaimer on last page. ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST6215C ST6225C 105/105 ...