ST72321J7 STMicroelectronics, ST72321J7 Datasheet - Page 32
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ST72321J7
Manufacturer Part Number
ST72321J7
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72321J7.pdf
(193 pages)
Specifications of ST72321J7
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST72321Rx ST72321ARx ST72321Jx
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the following features:
■
■
■
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
Figure 18. Interrupt Processing Flowchart
32/193
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management
with
management:
flexible
RESTORE PC, X, A, CC
FROM STACK
RESET
interrupt
priority
Y
and
INSTRUCTION
INTERRUPT
INSTRUCTION
FETCH NEXT
PENDING
EXECUTE
N
“IRET”
N
level
Y
each interrupt vector (see
ing flow is shown in
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
– The PC, X, A and CC registers are saved onto
– I1 and I0 bits of CC register are set according to
– The PC is then loaded with the interrupt vector of
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 6. Interrupt Software Priority Levels
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Interrupt software priority
the current instruction execution.
the stack.
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
STAYS PENDING
THE INTERRUPT
Interrupt has the same or a
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
lower software priority
than current one
STACK PC, X, A, CC
Figure 18
Table
Level
High
Low
TRAP
6). The process-
I1:0
N
I1
0
0
1
1
Y
I0
1
0
1
0
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