ST72324LK2 STMicroelectronics, ST72324LK2 Datasheet - Page 6
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ST72324LK2
Manufacturer Part Number
ST72324LK2
Description
3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324LK2.pdf
(154 pages)
Specifications of ST72324LK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
16-bit Timer A With
1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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ST72324Lxx
1 DESCRIPTION
The ST72F324L and ST72324BL devices are
members of the ST7 microcontroller family de-
signed for mid-range applications running at 3.3V.
Different package options offer up to 32 I/O pins.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with Flash or ROM pro-
gram memory. The ST7 family architecture offers
both power and flexibility to software developers,
Figure 1. Device Block Diagram
6/154
(6 bits on J and S devices)
(2 bits on K devices)
(6 bits on J and S devices)
(5 bits on K devices)
PF7:6,4,2:0
RESET
OSC1
OSC2
V
V
(2 bits)
PD5:0
PE1:0
AREF
V
V
V
SSA
DD
SS
PP
MCC/RTC/BEEP
8-BIT CORE
10-BIT ADC
CONTROL
TIMER A
PORT E
PORT D
PORT F
BEEP
OSC
ALU
SCI
enabling the design of highly efficient and compact
application code.
The on-chip peripherals include an A/D converter,
2 general purpose timers, an SPI interface and an
SCI interface.
For power economy, microcontroller can switch
dynamically into WAIT, SLOW, ACTIVE-HALT or
HALT mode when the application is in idle or
stand-by state.
Typical applications are consumer, home, office
and industrial products.
(384 - 2048 Bytes)
(8K - 32K Bytes)
WATCHDOG
PROGRAM
MEMORY
TIMER B
PORT C
PORT B
PORT A
RAM
SPI
(5 bits on J and S devices)
(3 bits on K devices)
(5 bits on J and S devices)
(4 bits on K devices)
PA7:3
(8 bits)
PC7:0
PB4:0
3
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