STM8L151C6 STMicroelectronics, STM8L151C6 Datasheet - Page 91

• Manufacturer Part Number: STM8L151C6
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L151C6

• Temp. Range: - 40 °C to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with full RTC (1.3 μA), Halt (350 nA)
• Consumption: 195 μA/MHz+440μA
• Ultralow Leakage Per I/0: 50 nA
• Fast Wakeup From Halt: 4.7 μs
• Lcd: up to 4x28 segments w/ step-up converter
• 4 Channels; Supported Peripherals: ADC, DAC, SPI, I2C, USART, timers
• 2 Watchdogs: 1 Window, 1 Independent

STM8L151xx, STM8L152xx
9.3.8
Table 43.
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
t
h(NSS)
t
su(MI)
t
v(SO)
v(MO)
h(MO)
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(2)(3)
(2)
(2)(4)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
conditions summarized in
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
SPI1 characteristics
SPI1 clock frequency
SPI1 clock rise and fall
time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Section
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode,
f
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
MASTER
Doc ID 15962 Rev 9
9.3.1. Refer to I/O port characteristics for more details on
= 8 MHz, f
Conditions
SYSCLK
SCK
(1)
= 4 MHz
frequency and V
Table 43
4 x 1/f
are derived from tests
Min
105
80
30
15
30
15
0
3
0
1
SYSCLK
0
-
-
-
-
DD
supply voltage
Electrical parameters
3x 1/f
Max
145
30
60
20
SYSCLK
8
8
-
-
-
-
-
-
-
-
-
91/126
Unit
MHz
ns