STM8L162R8 STMicroelectronics, STM8L162R8 Datasheet - Page 7

• Manufacturer Part Number: STM8L162R8
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L162R8

• Operating Power Supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
• Temperature Range: − 40 to 85 or 125 °C
• 5 Low Power Modes: Wait, Low power run, Low power wait, Active-halt with RTC, Halt
• Ultralow Leakage Per I/0: 50 nA
• Fast Wakeup From Halt: 5 μs
• Max Freq: 16 MHz, 16 CISC MIPS peak
• Lcd: 8x40 or 4x44 w/ step-up converter

STM8L162R8, STM8L162M8
List of figures
Figure 1.
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Figure 42.
Figure 43.
Figure 44.
High density STM8L162xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM8L162M8 80-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM8L162R8 64-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical I
Typical I
Typical I
Typical I
Typical I
Typical I
Typical IDD(AH) vs. V
Typical IDD(Halt) vs. V
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical HSI frequency vs. V
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical pull-up resistance R
Typical pull-up current I
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical NRST pull-up resistance R
Typical NRST pull-up current I
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI1 timing diagram - slave mode and CPHA=1
SPI1 timing diagram - master mode
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Power supply and reference decoupling (V
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 112
80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 118
Recommended footprint
DD(RUN)
DD(RUN)
DD(Wait)
DD(Wait)
DD(LPR)
DD(LPW)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
vs. V
from RAM vs. V
from Flash (HSI clock source), f
from RAM vs. V
from Flash vs. V
vs. V
DD
DD
DD
DD
pu
(1)
(LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 75
(LSI clock source), all peripherals OFF
(LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 81
vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
DD
PU
Doc ID 17959 Rev 2
pu
vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DD
DD
DD
vs. V
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PU
(HSI clock source), f
(1)
(HSI clock source), f
DD
(HSI clock source), f
vs. V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
REF+
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(1)
not connected to V
CPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
= 16 MHz
CPU
CPU
CPU
= 16 MHz
=16 MHz
= 16 MHz
1)
(1)
. . . . . . . . . . . . . . . . . . . 73
DDA
. . . . . . . . . . . . . . . . . 77
1) . . . . . . . . . . . . . . . . . 70
). . . . . . . . . . . . . 112
1)
1) . . . . . . . . . . . . . . . . 70
. . . . . . . . . . . . . 73
List of figures
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