STM8S207RB STMicroelectronics, STM8S207RB Datasheet - Page 41

• Manufacturer Part Number: STM8S207RB
• Description: Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM
• Manufacturer: STMicroelectronics

Specifications of STM8S207RB

• Max Fcpu: up to 24 MHz, 0 wait states @ fCPU≤ 16 MHz
• Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
• Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles
• Ram: up to 6 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

STM8S207xx, STM8S208xx
Table 9.
0x00 5331 to
0x00 5347 to
0x00 5408 to
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 53FF
0x00 532F
0x00 5330
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 541F
0x00 5420
0x00 5421
0x00 5422
0x00 5423
0x00 5424
0x00 5425
0x00 5426
0x00 5427
Address
General hardware register map (continued)
beCAN
Block
ADC2
TIM3
TIM4
Register label
TIM3_CCR1H
TIM3_CCR2H
TIM3_CCR1L
TIM3_CCR2L
TIM3_ARRH
TIM4_CNTR
TIM4_PSCR
TIM3_ARRL
ADC_TDRH
CAN_FPSR
ADC_TDRL
TIM4_EGR
ADC _CSR
TIM4_CR1
TIM4_ARR
ADC_DRH
CAN_MCR
CAN_MSR
CAN_DGR
CAN_RFR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRL
CAN_TSR
CAN_TPR
TIM4_IER
CAN_IER
TIM4_SR
Doc ID 14733 Rev 12
Reserved area (185 bytes)
Reserved area (15 bytes)
Reserved area (24 bytes)
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 2 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 low
TIM4 event generation register
TIM3 auto-reload register high
TIM4 interrupt enable register
TIM3 auto-reload register low
CAN interrupt enable register
CAN transmit priority register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
CAN transmit status register
CAN page selection register
CAN master control register
CAN master status register
ADC control/status register
CAN receive FIFO register
TIM4 auto-reload register
TIM4 prescaler register
CAN diagnosis register
ADC data register high
TIM4 control register 1
ADC data register low
TIM4 status register
Register name
TIM4 counter
Memory and register map
status
Reset
0xXX
0xXX
0x0C
0x0C
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x02
0x00
0x00
0x00
0x00
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