STM8AF52AA STMicroelectronics, STM8AF52AA Datasheet - Page 55
STM8AF52AA
Manufacturer Part Number
STM8AF52AA
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet
1.STM8AF5168.pdf
(106 pages)
Specifications of STM8AF52AA
Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
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STM8AF52/62xx, STM8AF51/61xx
Table 20.
Option byte no.
OPT10
OPT11
OPT3
OPT4
OPT5
OPT6
OPT7
OPT8
OPT9
Option byte description (continued)
LSI_EN: Low speed internal clock enable
IWDG_HW: Independent watchdog
WWDG_HW: Window watchdog activation
WWDG_HALT: Window watchdog reset on Halt
EXTCLK: External clock selection
CKAWUSEL: Auto-wakeup unit/clock
PRSC[1:0]: AWU clock prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
TMU[3:0]: Enable temporary memory unprotection
WAIT STATE: Wait state configuration
TMU_KEY 1 [7:0]: Temporary unprotection key 0
TMU_KEY 2 [7:0]: Temporary unprotection key 1
TMU_KEY 3 [7:0]: Temporary unprotection key 2
TMU_KEY 4 [7:0]: Temporary unprotection key 3
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
This configures the stabilization time to 0.5, 8, 128, and 2048 HSE
cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and
0x00.
0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
0: No wait state
1: One wait state
Temporary unprotection key: Must be different from 0x00 or 0xFF
Temporary unprotection key: Must be different from 0x00 or 0xFF
Temporary unprotection key: Must be different from 0x00 or 0xFF
Temporary unprotection key: Must be different from 0x00 or 0xFF
Doc ID 14395 Rev 8
Description
Option bytes
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