STM32F103VE STMicroelectronics, STM32F103VE Datasheet - Page 95

• Manufacturer Part Number: STM32F103VE
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 512 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103VE

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F103xC, STM32F103xD, STM32F103xE
I
Unless otherwise specified, the parameters given in
are derived from tests performed under ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 53.
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
2
DuCy(SCK)
S - SPI characteristics
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
the data.
the data in Hi-Z
t
t
h(NSS)
t
su(MI)
t
v(SO)
v(MO)
h(MO)
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
Section 5.3.14: I/O port characteristics
(1)
(1)
(1)
(1)
(1)
(1)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Doc ID 14611 Rev 8
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Table
10.
for more details on the input/output alternate
Conditions
PCLK
PCLK
Table 53
= 20 MHz
= 36 MHz,
for SPI or in
PCLKx
Electrical characteristics
frequency and V
4t
2t
Min
PCLK
PCLK
30
15
50
5
5
5
4
2
2
0
Table 54
3t
2
Max
S).
PCLK
18
70
60
10
25
18
5
8
for I
DD
95/130
MHz
Unit
2
ns
ns
%
S