STM32F205VC STMicroelectronics, STM32F205VC Datasheet - Page 87
STM32F205VC
Manufacturer Part Number
STM32F205VC
Description
High-performance ARM Cortex-M3 MCU with 256 Kbytes Flash, 120 MHz CPU, ART Accelerator
Manufacturer
STMicroelectronics
Datasheet
1.STM32F205VE.pdf
(170 pages)
Specifications of STM32F205VC
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
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STM32F205xx, STM32F207xx
Table 32.
1. TBD stands for “to be defined”.
2. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Guaranteed by design, not tested in production.
4. Value given with main PLL running.
5. Based on characterization, not tested in production.
Jitter
I
I
DD(PLLI2S)
DDA(PLLI2S)
Symbol
(4)
(5)
(5)
PLLI2S (audio PLL) characteristics
Master I2S clock jitter
WS I2S clock jitter
PLLI2S power consumption on
V
PLLI2S power consumption on
V
DD
DDA
Parameter
Doc ID 15818 Rev 8
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
Average frequency of
12,343 MHz
N=432, P=4, R=5
on 256 samples
Cycle to cycle at 48 KHz
on 1000 samples
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
(1)
(continued)
Conditions
RMS
peak
peak
to
0.30
0.55
TBD
0.15
0.45
Min
-
-
-
Electrical characteristics
±280
Typ
400
90
-
-
-
TBD
Max
0.40
0.75
0.40
0.85
-
-
-
87/170
Unit
mA
mA
ps
ps
ps