STM32F205ZC STMicroelectronics, STM32F205ZC Datasheet - Page 23
STM32F205ZC
Manufacturer Part Number
STM32F205ZC
Description
High-performance ARM Cortex-M3 MCU with 256 Kbytes Flash, 120 MHz CPU, ART Accelerator
Manufacturer
STMicroelectronics
Datasheet
1.STM32F205VE.pdf
(170 pages)
Specifications of STM32F205ZC
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
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STM32F205xx, STM32F207xx
2.2.16
a.
Voltage regulator
The regulator has five operating modes:
●
●
Regulator ON
The regulator ON modes are activated by default on LQFP packages.On WLCSP66
package, they are activated by connecting both REGOFF and IRROFF pins to V
only REGOFF must be connected to V
V
There are three regulator ON modes:
●
●
●
Regulator OFF
●
V
temperature range.
DD
DD
/V
minimum value is 1.8 V
Regulator ON
–
–
–
Regulator OFF
–
–
MR is used in nominal regulation mode (Run)
LPR is used in Stop mode
Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF/internal reset ON
On WLCSP66 package, this mode is activated by connecting REGOFF pin to V
IRROFF pin to V
(IRROFF not available).
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
DDA
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
Regulator OFF/internal reset ON
Regulator OFF/internal reset OFF
V
between power domains.
If the time for V
reach 1.8 V
minimum value of 1.65 V is obtained when the device operates in a reduced
DD
should always be higher than V
(a)
SS
CAP_1
, then PA0 should be connected to the NRST pin (see
. On UFBGA176 package, only REGOFF must be connected to V
CAP_1
(a)
and V
.
Doc ID 15818 Rev 8
and V
CAP_2
CAP_2
SS
pins, in addition to V
on UFBGA176 package (IRROFF is not available).
to reach 1.08 V is faster than the time for V
CAP_1
and V
CAP_2
DD
.
to avoid current injection
Figure
Description
SS
, while
DD
7).
23/170
DD
and
DD
to