STM32F217ZE STMicroelectronics, STM32F217ZE Datasheet - Page 162

• Manufacturer Part Number: STM32F217ZE
• Description: High-performance ARM Cortex-M3 MCU with 512 Kbytes Flash, 120 MHz CPU, ART Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F217ZE

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Revision history
162/168
Table 91.
22-Apr-2011
Date
Document revision history (continued)
Revision
4
Changed datasheet status to “Full Datasheet”.
APB1 frequency changed form 36 MHz to 30 MHz.
Introduced concept of SRAM1 and SRAM2.
LQFP176 now in production.
Removed WLCSP64+2 package.
Updated
and STM32F2xx for LQFP144 package
board design between STM32F10xx and STM32F2xx for LQFP100
package.
Added camera interface for STM32F217Vx devices in
STM32F215xx and STM32F217xx: features and peripheral
Removed 16 MHz internal RC oscillator accuracy in
Clocks and
Updated
Modified I
and
Section 2.2.30: Audio PLL
Updated
backup registers
General-purpose timers
Modified maximum baud rate (oversampling by 16) for USART1 in
Table 4: USART feature
Updated note related to RFU pin below
LQFP100
STM32F21x LQFP176
ballout, and
Added RTC_50Hz as PB15 alternate function, and TT (3.6 V tolerant
I/O) in
Alternate function
PA15 added in
In
I2S3_CK to I2S2_SCK and I2S3_SCK, respectively.
Removed ETH _RMII_TX_CLK for PC3/AF11 in
function
Updated
characteristics.
T
Added CEXT and ESR in
well as
Modified
power supply
Updated
(regulator
power-down (regulator
Added OSC_OUT pin in
Figure 16: Pin input
Updated notes below
Updated V
I
power control block
RUSH
STG
Table 5: STM32F21x pin and ball
Doc ID 17050 Rev 6
startup,
updated to –65 to +150 in
, added E
Table 5: STM32F21x pin and ball definitions
Section 5.3.2: VCAP1/VCAP2 external
mapping.
Figure 3: Compatible board design between STM32F10xx
Section 2.2.16: Voltage
Section 2.2.17: Real-time clock (RTC), backup SRAM and
Table 7: Voltage characteristics
Note 3
Table 13: Operating conditions at power-up / power-down
2
pinout,
ON), and
PVD
S sampling frequency range in
startup.
Table 5: STM32F21x pin and ball
Section 2.2.24: Inter-integrated sound
range.
, V
Table 5: STM32F21x pin and ball
RUSH
in
BOR1
and description of TIM2 and TIM5 in
Figure 11: STM32F21x LQFP144
mapping.
Table 11: Limitations depending on the operating
characteristics.
Table 14: Operating conditions at power-up /
voltage.
and
Figure 15: Pin loading
, V
pinout,
OFF).
comparison.
(TIMx).
BOR2
Figure 15: Pin loading
Note 3
Table 10: General operating conditions
(PLLI2S).
, V
Changes
Figure 13: STM32F21x UFBGA176
Table 9: Thermal
BOR3
in
regulator.
Table 15: Embedded reset and
definitions, changed I2S2_CK and
STM32F215xx, STM32F217xx
, T
Figure 10: STM32F21x
RSTTEMPO
and
and
Figure 2: Compatible
conditions.
Table 6: Alternate
Table 8: Current
Section 2.2.12: Clocks
definitions.
capacitor.
conditions. and
definitions.
characteristics.
typical value, and
(I2S), and
and
pinout,
Section 2.2.12:
Table 2:
Section :
Table 6:
Figure 12:
counts.
as