STM32F103RC STMicroelectronics, STM32F103RC Datasheet - Page 17
STM32F103RC
Manufacturer Part Number
STM32F103RC
Description
Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Manufacturer
STMicroelectronics
Datasheet
1.STM32F103RC.pdf
(130 pages)
Specifications of STM32F103RC
Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
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STM32F103xC, STM32F103xD, STM32F103xE
2.3.10
2.3.11
2.3.12
2.3.13
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics
V
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
This regulator is always enabled after reset. It is disabled in Standby mode.
DD
POR/PDR
/V
Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
Boot from system memory
Boot from embedded SRAM
V
Provided externally through V
V
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
is used). V
V
registers (through power switch) when V
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop modes.
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
DD
SSA
BAT
DDA
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
PVD
and V
power supply and compares it to the V
DDA
threshold. The interrupt service routine can then generate a warning
DDA
PVD
= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
DD
and V
.
/V
DD
DDA
is below a specified threshold, V
SSA
drops below the V
must be connected to V
Doc ID 14611 Rev 8
DD
pins.
DD
PVD
is not present.
PVD
threshold and/or when V
threshold. An interrupt can be
DD
Figure 12: Power supply
and V
POR/PDR
SS
, respectively.
, without the need for an
for the values of
DD
/V
DDA
Description
scheme.
is higher
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