5M160ZT100C4N Altera Corporation, 5M160ZT100C4N Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/0/41/altera_corporation_sml.jpg)
5M160ZT100C4N
Manufacturer Part Number
5M160ZT100C4N
Description
IC MAX V CPLD 160 LE 100-TQFP
Manufacturer
Altera Corporation
Series
MAX® Vr
Datasheet
1.5M240ZT100C5N.pdf
(30 pages)
Specifications of 5M160ZT100C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Lead Free Status
Vendor undefined
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M160ZT100C4N
Manufacturer:
ALTERA
Quantity:
200
3–22
Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device
Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device
MAX V Device Handbook
t
t
t
t
t
t
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Only applicable to the F324 package of the 5M1270Z device.
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
Symbol
Symbol
clock input pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
3–31:
3–30:
Table 3–30
5M1270Z device.
Table 3–31
Parameter
Parameter
lists the external I/O timing parameters for the F324 package of the
lists the external I/O timing parameters for the 5M2210Z device.
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 3: DC and Switching Characteristics for MAX V Devices
Min
216
Min
216
216
216
2.0
2.0
1.5
4.0
1.5
4.0
—
—
—
—
—
—
0
0
C4
C4
(Note
(Note 1)
247.5
247.5
Max
Max
9.1
4.8
6.0
9.1
4.8
6.0
—
—
—
—
—
—
—
—
—
—
1),
(2)
Timing Model and Specifications
Min
Min
266
266
266
266
May 2011 Altera Corporation
1.9
2.0
5.0
1.9
2.0
5.0
—
—
—
—
—
—
0
0
C5, I5
C5, I5
201.1
201.1
Max
11.2
Max
11.2
5.9
7.4
5.9
7.4
—
—
—
—
—
—
—
—
—
—
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
ps
ns