5M160ZT100C4N Altera Corporation, 5M160ZT100C4N Datasheet - Page 12
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5M160ZT100C4N
Manufacturer Part Number
5M160ZT100C4N
Description
IC MAX V CPLD 160 LE 100-TQFP
Manufacturer
Altera Corporation
Series
MAX® Vr
Datasheet
1.5M240ZT100C5N.pdf
(30 pages)
Specifications of 5M160ZT100C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Lead Free Status
Vendor undefined
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M160ZT100C4N
Manufacturer:
ALTERA
Quantity:
200
3–12
Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)
Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)
MAX V Device Handbook
UFM
Notes to
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I
t
t
t
t
t
t
t
Resource
LUT
COMB
CLR
PRE
SU
H
CO
Symbol
Used
Table
2
C megafunction is verified in hardware up to 100-kHz serial clock line rate.
Internal Timing Parameters
LE combinational look-up
table (LUT) delay
Combinational path delay
LE register clear delay
LE register preset delay
LE register setup time
before clock
LE register hold time
after clock
LE register
clock-to-output delay
512 × 16
512 × 16
512 × 8
512 × 16
3–17:
f
Design Size and
Function
Parameter
Internal timing parameters are specified on a speed grade basis independent of device
density.
timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and
MultiTrack interconnects.
For more information about each internal timing microparameters symbol, refer to
AN629: Understanding Timing in Altera
Table 3–18
SPI
Parallel
I
Mode
2
None
C
(3)
(3)
(2)
Resources Used
Min
401
401
260
—
—
—
0
through
5M40Z/ 5M80Z/ 5M160Z/
C4
142
LEs
37
73
3
5M240Z/ 5M570Z
1,215
Max
243
380
—
—
—
—
Table 3–25 on page 3–19
Blocks
UFM
1
1
1
1
Min
545
545
321
—
—
—
0
5M40Z/ 5M80Z/ 5M160Z/
C5, I5
Chapter 3: DC and Switching Characteristics for MAX V Devices
100
CPLDs.
10.0
5M240Z/ 5M570Z
9.7
C4
(4)
2,247
Max
309
494
(5)
—
—
—
—
100
Min
309
309
271
C5, I5
10.0
—
—
—
0
9.7
(4)
list the MAX V device internal
Performance
(5)
C4
5M1270Z/ 5M2210Z
Max
742
192
305
—
—
—
—
100
Timing Model and Specifications
5M1270Z/ 5M2210Z
10.0
May 2011 Altera Corporation
8.0
C4
(4)
(5)
Min
381
381
333
—
—
—
0
C5, I5
100
C5, I5
10.0
8.0
(4)
Max
914
236
376
—
—
—
—
(5)
Unit
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
ps
ps
kHz