EP4CE6F17C6N Altera Corporation, EP4CE6F17C6N Datasheet - Page 24
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EP4CE6F17C6N
Manufacturer Part Number
EP4CE6F17C6N
Description
IC CYCLONE IV FPGA 6K 256FBGA
Manufacturer
Altera Corporation
Series
CYCLONE® IV Er
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CE6F17C6N
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
276480
Number Of I /o
179
Number Of Gates
-
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE6F17C6N
Manufacturer:
ALTERA
Quantity:
319
1–24
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 2 of 2)—Preliminary
Table 1–25. PLL Specifications for Cyclone IV Devices
Cyclone IV Device Handbook,
Volume 3
EP4CE55
EP4CE75
EP4CE115
EP4CGX15
EP4CGX22
EP4CGX30
EP4CGX50
EP4CGX75
EP4CGX110
EP4CGX150
Note to
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.
f
f
f
f
t
f
output)
f
t
t
IN
INPFD
VCO
INDUTY
INJITTER_CCJ
OUT_EXT
OUT
OUTDUTY
LOCK
Device
(3)
(to global clock)
(4)
Table
(external clock
(3)
Symbol
(5)
1–24:
500
500
500
500
500
500
500
500
500
C6
—
PLL Specifications
Table 1–25
commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), the extended industrial junction temperature
range (–40°C to 125°C), and the automotive junction temperature range (–40°C to
125°C). For more information about the PLL block, refer to
Input clock frequency (–6, –7, –8 speed grades)
Input clock frequency (–8L speed grade)
Input clock frequency (–9L speed grade)
PFD input frequency
PLL internal VCO operating range
Input clock duty cycle
Input clock cycle-to-cycle jitter
F
F
PLL output frequency
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
PLL output frequency (–8L speed grade)
PLL output frequency (–9L speed grade)
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
REF
REF
C7
100 MHz
< 100 MHz
lists the PLL specifications for Cyclone IV devices when operating in the
402
402
402
402
402
402
402
402
402
402
C8
Parameter
C8L
(1), (2)
362
362
362
—
—
—
—
—
—
—
Performance
(1)
(Part 1 of 2)—Preliminary
C9L
265
265
265
—
—
—
—
—
—
—
(1)
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
I7
Min
600
Chapter 1: Cyclone IV Device Datasheet
40
—
—
—
—
—
—
—
—
45
—
5
5
5
5
“Glossary” on page
November 2011 Altera Corporation
I8L
362
362
362
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
(1)
Switching Characteristics
472.5
472.5
472.5
402.5
1300
±750
Max
0.15
362
265
325
450
362
265
60
55
1
A7
—
—
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
1–38.
ms
UI
ps
%
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit