PHK18NQ03LT NXP Semiconductors, PHK18NQ03LT Datasheet
PHK18NQ03LT
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PHK18NQ03LT Summary of contents
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... PHK18NQ03LT N-channel TrenchMOS logic level FET Rev. 03 — 17 March 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...
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... ° j(init) ≤ unclamped sup = 50 Ω All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Graphic symbol mbb076 Version SOT96-1 Min Max - kΩ ...
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... P (%) 150 200 T (°C) sp Fig All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET 120 der 100 Normalized total power dissipation as a function of solder point temperature 10 μ 100 μ ...
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... Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration PHK18NQ03LT Product data sheet Conditions - All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Min Typ Max - - 20 003aaa681 t p δ ...
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... MHz °C; see Figure 0.8 Ω 5.6 Ω R G(ext) All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Min Typ Max 1.3 1.7 2.15 0 ...
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... C rss 1 -60 V (V) GS Fig 8. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Min Typ - 0. 003aaa683 = 150 °C 25 ° ...
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... Fig 10. Normalized drain-source on-state resistance 003aaa684 3 3.2 3.4 4 (A) D Fig 12. Gate charge waveform definitions All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET 2 0 − 120 factor as a function of junction temperature GS(pl) ...
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... Fig 14. Input, output and reverse transfer capacitances ( 150 ° 0 All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET (pF MHz function of drain-source voltage ...
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... REFERENCES JEDEC JEITA MS-012 All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET θ detail ...
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... Product data sheet Data sheet status Change notice Product data sheet - Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Supersedes PHK18NQ03LT v.2 PHK18NQ03LT v.1 © NXP B.V. 2011. All rights reserved ...
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... In case an individual agreement is concluded only the terms and conditions of the respective All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...
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... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 17 March 2011 PHK18NQ03LT N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2011. All rights reserved ...
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... Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.4 Trademarks .12 10 Contact information .12 PHK18NQ03LT N-channel TrenchMOS logic level FET Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...