PHD71NQ03LT NXP Semiconductors, PHD71NQ03LT Datasheet
PHD71NQ03LT
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PHD71NQ03LT Summary of contents
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... PHD71NQ03LT N-channel TrenchMOS logic level FET Rev. 02 — 9 March 2010 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...
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... Figure 2 mb pulsed; δ ≤ 50 µ °C mb ≤ 10 µs; pulsed ° All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET Graphic symbol Min - - -20 Figure 1 - and 3 - ...
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... Fig DSon All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET 120 P der (%) 100 Normalized total power dissipation as a function of mounting base temperature 03ai76 = 10 μ ...
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... PHD71NQ03LT_2 Product data sheet Conditions see Figure 4 mounted on a printed-circuit board; minimum footprint single pulse −4 − All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET Min Typ Max - - 1. 03ai75 t p δ = ...
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... °C; see /dt = -100 A/µ ° All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET Min Typ Figure 8 0.6 - Figure Figure 8 1 1.9 - ...
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... 0.6 0 (V) DS Fig 6. 03ai28 typ max 2.4 3.2 V (V) GS Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET 80 × > DSon 175 °C = ° ...
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... Fig 10. Normalized drain-source on-state resistance 03ai82 (nC) G Fig 12. Input, output and reverse transfer capacitances All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET 2 a 1.5 1 0 factor as a function of junction temperature ...
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... PHD71NQ03LT_2 Product data sheet ( 175 ° 0.3 0.6 All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET 03ai80 = 25 ° 0.9 1.2 V (V) SD © NXP B.V. 2010. All rights reserved ...
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... min min 5.46 0.56 6.22 6.73 4.0 4.45 5.00 0.20 5.98 6.47 REFERENCES JEDEC JEITA SC-63 TO-252 All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET min 10.4 2.95 2.285 4.57 0.5 9.6 2.55 EUROPEAN PROJECTION SOT428 ...
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... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Type number PHD71NQ03LT separated from data sheet PHP_PHB_PHD71NQ03LT-01. Product data All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 9 March 2010 PHD71NQ03LT N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PHD71NQ03LT_2 All rights reserved. Date of release: 9 March 2010 ...