P89LPC920_921_922_9221 NXP Semiconductors, P89LPC920_921_922_9221 Datasheet - Page 22

• Manufacturer Part Number: P89LPC920_921_922_9221
• Description: The P89LPC920/921/922/9221 are single-chip microcontrollers designed forapplications demanding high-integration, low cost solutions over a wide range ofperformance requirements
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14469
Product data
8.14.1 Idle mode
8.14.2 Power-down mode
8.14.3 Total Power-down mode
8.15 Reset
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.
The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC920/921/922/9221 exits Power-down mode via any reset, or certain
interrupts. In Power-down mode, the power supply voltage may be reduced to the
RAM keep-alive voltage V
Power-down mode was entered. SFR contents are not guaranteed after V
been lowered to V
via reset in this case. V
Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock AND
the RTC is enabled.
This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: During a power cycle, V
characteristics” on page
reset.
Reset can be triggered from the following sources:
Rev. 08 — 15 December 2004
RAM
, therefore it is highly recommended to wake up the processor
DD
36) before power is reapplied, in order to ensure a power-on
RAM
must be raised to within the operating range before the
. This retains the RAM contents at the point where
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
DD
must fall below V
POR
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(see
Table 8 “DC electrical
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has
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