LPC1788FET208 NXP Semiconductors, LPC1788FET208 Datasheet - Page 59

The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1788FET208

Manufacturer Part Number
LPC1788FET208
Description
The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
Manufacturer
NXP Semiconductors
Datasheet

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LPC178X_7X
Objective data sheet
7.30.1 Features
7.31.1 Features
7.30 Windowed WatchDog Timer (WWDT)
7.31 RTC and backup registers
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. The RTC on the LPC178x/7x is designed to have extremely low power
consumption, i.e. less than 1 A. The RTC will typically run from the main chip power
supply conserving battery power while the rest of the device is powered up. When
operating from a battery, the RTC will continue working down to 2.1 V. Battery power can
be provided from a standard 3 V lithium button cell.
An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion
of the RTC, moving most of the power consumption out of the time counting function.
The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way
that will provide less than 1 second per day error when operated at a constant voltage and
temperature.
The RTC contains a small set of backup registers (20 bytes) for holding data while the
main part of the LPC178x/7x is powered off.
The RTC includes an alarm function that can wake up the LPC178x/7x from all reduced
power modes with a time resolution of 1 s.
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is
always running if the watchdog timer is enabled.
Measures the passage of time to maintain a calendar and clock.
Ultra low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 3 — 27 December 2011
 4.
cy(WDCLK)
 256  4) to (T
32-bit ARM Cortex-M3 microcontroller
cy(WDCLK)
LPC178x/7x
 2
© NXP B.V. 2011. All rights reserved.
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 4) in
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