LPC11E11FHN33 NXP Semiconductors, LPC11E11FHN33 Datasheet
LPC11E11FHN33
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LPC11E11FHN33 Summary of contents
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LPC11E1x 32-bit ARM Cortex-M0 microcontroller flash SRAM and 4 kB EEPROM; USART Rev. 1 — 20 February 2012 1. General description The LPC11E1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, ...
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... NXP Semiconductors Digital peripherals: General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode. GPIO pins can be selected as edge and level sensitive interrupt sources. Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. ...
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... LQFP48 LPC11E14FHN33/401 HVQFN33 LPC11E14FBD48/401 LQFP48 LPC11E14FBD64/401 LQFP64 4.1 Ordering options Table 2. Part Number LPC11E11FHN33/101 LPC11E12FBD48/201 16 kB LPC11E13FBD48/301 24 kB LPC11E14FHN33/401 32 kB LPC11E14FBD48/401 32 kB LPC11E14FBD64/401 32 kB LPC11E1X Product data sheet Description plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 7 0.85 mm plastic low profile quad flat package ...
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... NXP Semiconductors 5. Block diagram LPC11E1x HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) DCD, DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 (2) CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 (2) CT16B1_CAP[1:0] CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (2) CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (2) CT32B1_CAP[1:0] WINDOWED WATCHDOG ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration (HVQFN33) LPC11E1X Product data sheet terminal 1 index area LPC11E11 XTALIN 4 LPC11E14 XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO1_25/CT32B0_MAT1 PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_26/CT32B0_MAT2/RXD PIO1_27/CT32B0_MAT3/TXD Fig 3. Pin configuration (LQFP48) LPC11E1X Product data sheet LPC11E12FBD48/201 6 LPC11E13FBD48/301 7 LPC11E14FBD48/401 All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 February 2012 ...
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... NXP Semiconductors PIO1_0 1 PIO1_25 2 3 PIO1_19 4 RESET/PIO0_0 PIO0_1 5 PIO1_7 XTALIN 9 XTALOUT PIO0_20 11 PIO1_10 12 13 PIO0_2 14 PIO1_26 PIO1_27 15 PIO1_4 16 See Table 3 for the full pin name. Fig 4. Pin configuration (LQFP64) LPC11E1X Product data sheet LPC11E14FBD64/401 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 3 port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO0_8/MISO0/ 17 CT16B0_MAT0 PIO0_9/MOSI0/ 18 CT16B0_MAT1 SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 TDI/PIO0_11/AD0/ 21 CT32B0_MAT3 TMS/PIO0_12/AD1/ 22 CT32B1_CAP0 TDO/PIO0_13/AD2/ 23 CT32B1_MAT0 TRST/PIO0_14/AD3/ 24 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 25 CT32B1_MAT2 PIO0_16/AD5/ 26 CT32B1_MAT3/WAKEUP LPC11E1X Product data sheet Reset Type Description state [1] [ I/O PIO0_8 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO0_17/RTS/ 30 CT32B0_CAP0/SCLK PIO0_18/RXD/ 31 CT32B0_MAT0 PIO0_19/TXD/ 32 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 7 PIO0_21/CT16B1_MAT0/ 12 MOSI1 PIO0_22/AD6/ 20 CT16B1_MAT1/MISO1 PIO0_23/AD7 27 PIO1_0/CT32B1_MAT0 - PIO1_1/CT32B1_MAT1 - PIO1_2/CT32B1_MAT2 - PIO1_3/CT32B1_MAT3 - PIO1_4/CT32B1_CAP0 - PIO1_5/CT32B1_CAP1 - PIO1_6 - PIO1_7 - LPC11E1X Product data sheet Reset Type Description state [1] [ I/O PIO0_17 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO1_8 - PIO1_9 - PIO1_10 - PIO1_11 - PIO1_12 - PIO1_13/DTR/ - CT16B0_MAT0/TXD PIO1_14/DSR/ - CT16B0_MAT1/RXD PIO1_15/DCD/ 28 CT16B0_MAT2/SCK1 PIO1_16/RI/ - CT16B0_CAP0 PIO1_17/CT16B0_CAP1/ - RXD PIO1_18/CT16B1_CAP1/ - TXD PIO1_19/DTR/SSEL1 1 PIO1_20/DSR/SCK1 - PIO1_21/DCD/MISO1 - PIO1_22/RI/MOSI1 - LPC11E1X Product data sheet Reset Type Description state [1] [ I/O PIO1_8 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO1_23/CT16B1_MAT1/ 13 SSEL1 PIO1_24/CT32B0_MAT0 14 PIO1_25/CT32B0_MAT1 - PIO1_26/CT32B0_MAT2/ - RXD PIO1_27/CT32B0_MAT3/ - TXD PIO1_28/CT32B0_CAP0/ - SCLK PIO1_29/SCK0/ - CT32B0_CAP1 PIO1_31 - n.c. - n.c. - XTALIN 4 XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. ...
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... NXP Semiconductors [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see input glitch filter. [7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise) ...
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... NXP Semiconductors 7. Functional description 7.1 On-chip flash programming memory The LPC11E1x contain on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. 7.2 EEPROM The LPC11E1x contain 500 Byte, 1 kB on-chip byte-erasable and byte-programmable EEPROM data memory ...
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... NXP Semiconductors LPC11E1x 4 GB reserved private peripheral bus reserved GPIO reserved APB peripherals 1 GB reserved 2 kB SRAM (LPC11E14/401) 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC11E13/301 LPC11E14/401 SRAM (LPC11E12/201 SRAM (LPC11E11/101) reserved 32 kB on-chip flash (LPC11E14 on-chip flash (LPC11E13) ...
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... NXP Semiconductors • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source ...
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... NXP Semiconductors 7.8.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • ...
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... NXP Semiconductors • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 2 7.11 I C-bus serial I/O controller The LPC11E1x contain one I 2 The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA) ...
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... NXP Semiconductors • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.13 General purpose external event counter/timers The LPC11E1x include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
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... NXP Semiconductors • Optional warning interrupt can be generated at a programmable time before watchdog time-out. • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT. • Incorrect feed sequence causes reset or interrupt, if enabled. • Flag to indicate watchdog reset. ...
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... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) Fig 6. LPC11E1x clocking generation block diagram 7.16.1.1 Internal RC oscillator The IRC can be used as the clock source for the WDT, and/or as the clock that drives the system PLL and then the CPU. The nominal IRC frequency is 12 MHz. ...
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... NXP Semiconductors 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz ...
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... NXP Semiconductors 7.16.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution ...
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... NXP Semiconductors 7.16.6 System control 7.16.6.1 Reset Reset has four sources on the LPC11E1x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller ...
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... NXP Semiconductors CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11Exx user manual. 7.16.6.4 APB interface The APB peripherals are located on one APB bus. ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...
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... NXP Semiconductors Table 5. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) I LOW-level input current V ...
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... NXP Semiconductors Table 5. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter 2 I C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I LOW-level output OL current I input leakage current ...
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... NXP Semiconductors Table 6. ADC static characteristics +85 C unless otherwise specified; ADC frequency 4.5 MHz, V amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 9.1 BOD static characteristics Table amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC11Exx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see the LPC11Exx user manual): • ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC11E1X Product data sheet ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Typical supply current versus temperature in Sleep mode (µA) Fig 11. Typical supply current versus temperature in Deep-sleep mode LPC11E1X Product data sheet ...
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... NXP Semiconductors (µA) Fig 12. Typical supply current versus temperature in Power-down mode (µA) Fig 13. Typical supply current versus temperature in Deep power-down mode 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers ...
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... NXP Semiconductors Table 8. Peripheral IRC System oscillator at 12 MHz Watchdog oscillator at 500 kHz/2 BOD Main PLL ADC CLKOUT CT16B0 CT16B1 CT32B0 CT32B1 GPIO IOCONFIG I2C ROM SPI0 SPI1 UART WWDT LPC11E1X Product data sheet Power consumption for individual analog and digital blocks ...
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... NXP Semiconductors 9.4 Electrical pin characteristics V Fig 14. High-drive output: Typical HIGH-level output voltage V (mA) Fig 15. I LPC11E1X Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5. ...
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... NXP Semiconductors (mA) Fig 16. Typical LOW-level output current I V Fig 17. Typical HIGH-level output voltage V LPC11E1X Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) Fig 18. Typical pull-up current I (μA) Fig 19. Typical pull-down current I LPC11E1X Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 °C ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 9. amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Table 10. amb Failure rate < 10 ppm for parts as specified below. ...
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... NXP Semiconductors Fig 20. External clock timing (with an amplitude of at least V 10.3 Internal oscillators Table 12. amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors [2] The typical frequency spread over processing and temperature (T [3] See the LPC11Exx user manual. 10.4 I/O pins Table 14. amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 15. Dynamic characteristic: I [ +85 C ...
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... NXP Semiconductors [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t ...
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... NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC11E1X Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 February 2012 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC11E1X Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 February 2012 ...
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... NXP Semiconductors 11. Application information 11.1 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...
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... NXP Semiconductors Fig 26. Oscillator modes and models: oscillation mode of operation and external crystal Table 17. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 18. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.2 XTAL Printed-Circuit Board (PCB) layout guidelines Follow these guidelines for PCB layout: • ...
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... NXP Semiconductors • Connect the external components to the ground plain. • To keep parasitics and the noise coupled in via the PCB as small as possible, keep loops as small as possible. • Choose smaller values of C 11.3 Standard I/O pad configuration Figure 27 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.4 Reset pad configuration Fig 28. Reset pad configuration 11.5 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11E1x chip. ...
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... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 32. Reflow soldering for the HVQFN33 (7x7) package LPC11E1X Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5 ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 33. Reflow soldering for the LQFP48 package LPC11E1X Product data sheet (8× Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP64 package solder land occupied area DIMENSIONS 0.500 0.560 13.300 13.300 10.300 10.300 Fig 34. Reflow soldering for the LQFP64 package LPC11E1X Product data sheet Hx Gx (0.125 (8× ...
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... NXP Semiconductors 14. Abbreviations Table 19. Acronym A/D ADC AHB APB BOD BSDL GPIO JTAG PLL RC SPI SSI SSP TAP USART LPC11E1X Product data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection Boundary Scan Description Language ...
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... NXP Semiconductors 15. Revision history Table 20. Revision history Document ID Release date LPC11E1X v.1 20120220 LPC11E1X Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 February 2012 LPC11E1x 32-bit ARM Cortex-M0 microcontroller Change notice ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 On-chip flash programming memory . . . . . . . 14 7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 Memory map 7.6 Nested Vectored Interrupt Controller (NVIC ...