LPC11C12FBD48 NXP Semiconductors, LPC11C12FBD48 Datasheet - Page 19

• Manufacturer Part Number: LPC11C12FBD48
• Description: The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.10.1 Features
7.11.1 Features
7.11 C_CAN controller
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
On-chip C_CAN drivers provide an API for initialization and communication using CAN
and CANopen standards.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The I
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
2
2
C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
2
2
2
C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 June 2011
2
C-bus compliant interface with open-drain pins. The
32-bit ARM Cortex-M0 microcontroller
2
C is a multi-master bus and can be
LPC11Cx2/Cx4
© NXP B.V. 2011. All rights reserved.
19 of 62