STA304A STMicroelectronics, STA304A Datasheet - Page 19

• Manufacturer Part Number: STA304A
• Description: IC PROCESSOR AUD DGTL DDX 44TQFP
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Processorr

Specifications of STA304A

• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Case: QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -
• Other names: 497-3944

and read or write mode.
The 7 most significant bits are the device address identifier, corresponding to the I
In STA304A the I
0, and 0011111 when SA = 1.
The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After
a START condition the STA304A identifies on the bus the device address and, if a match is found, it acknowl-
edges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte
is the internal space address.
11.3 WRITE OPERATION
Following a START condition the master sends a device select code with the RW bit set to 0. The STA304A
acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the
STA304A again responds with an acknowledge.
11.3.1Byte write
In the byte write mode the master sends one data byte, this is acknowledged by STA304A. The master then
terminates the transfer by generating a STOP condition.
11.3.2Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master gener-
ating a STOP condition.
Figure 13. Write Mode Sequence
Figure 14. Read Mode Sequence
SEQUENTIAL
SEQUENTIAL
MULTIBYTE
CURRENT
ADDRESS
ADDRESS
CURRENT
RANDOM
RANDOM
READ
READ
READ
READ
WRITE
WRITE
BYTE
START
START
START
START
START
START
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEV-ADDR
2
C interface has two device address depending on SA pin configuration 0011110 when SA =
DEV-ADDR
DEV-ADDR
HIGH
RW=
RW
RW
RW
ACK
ACK
ACK
ACK
RW
RW
SUB-ADDR
SUB-ADDR
DATA
DATA
ACK
ACK
NO ACK
ACK
ACK
ACK
SUB-ADDR
SUB-ADDR
START
START
STOP
DATA
DEV-ADDR
DEV-ADDR
ACK
ACK
RW
RW
ACK
ACK
ACK
DATA IN
DATA IN
DATA
DATA
DATA
ACK
ACK
NO ACK
NO ACK
ACK
STOP
STOP
STOP
DATA
D98AU825B
2
C bus definition.
D98AU826A
ACK
DATA IN
DATA
STA304A
ACK
NO ACK
STOP
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STOP