E-TDA7590 STMicroelectronics, E-TDA7590 Datasheet - Page 10

• Manufacturer Part Number: E-TDA7590
• Description: IC DSP SPEECH/AUDIO 144-TQFP
• Manufacturer: STMicroelectronics
• Type: Signalr

Specifications of E-TDA7590

• Applications: Speech Recognition
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP Exposed Pad, 144-eTQFP, 144-HTQFP, 144-VQFP
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 384KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.62/3V
• Operating Supply Voltage (max): 1.98/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin description
Table 2.
10/42
N°
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
COREVDD
Pin function (continued)
COREVSS
WEN_N
OEN_N
HAD[6]
HAD[5]
HAD[4]
HAD[3]
HAD[2]
HAD[1]
HAD[0]
IOVDD
IOVDD
IOVSS
IOVSS
Name
BG_N
BR_N
BB_N
AA[3]
AA[2]
AA[1]
AA[0]
AB[0]
AB[1]
AB[2]
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Host 8-bit data line 6. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 5. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 4. Host data bus and/or address lines when in multiplexed
mode.
Core power supply.
Core ground.
Host 8-bit data line 3. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 2. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 1. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 0. Host data bus and/or address lines when in multiplexed
mode.
Address attributes line 3.Port A address attributes/chip select pins with
programmable polarity.
Address attributes line 2.Port A address attributes/chip select pins with
programmable polarity.
Bus request. Asserted when port A requires bus mastership to perform off-
chip accesses.
Bus busy. Asserted by port A when bus_busy_in_n is negated and BG_N is
asserted.
IO power supply.
IO ground.
Write enable.
Output enable.
Address attributes line 1.Port A address attributes/chip select pins with
programmable polarity.
Address attributes line 0.Port A address attributes/chip select pins with
programmable polarity.
Bus grant. When asserted, Port A becomes the bus master elect. Bus
mastership
is attained when bus busy is negated by the current bus master.
Address bus line 0. Port A external address bus.
Address bus line 1. Port A external address bus.
IO power supply.
IO ground.
Address bus line 2. Port A external address bus.
Description
TDA7590