TDA7348D013TR STMicroelectronics, TDA7348D013TR Datasheet - Page 10

• Manufacturer Part Number: TDA7348D013TR
• Description: IC PROCESSOR AUDIO DGTL SO-28
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of TDA7348D013TR

• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -

I
3
3.1
3.2
3.3
3.4
3.5
10/20
2
C BUS interface
I
Data transmission from microprocessor to the TDA7348 and vice-versa takes place through
the 2 wires of the I
resistors to the positive supply voltage must be externally connected).
Data validity
As shown in
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Start and stop conditions
As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
A STOP conditions must be sent before each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
Transmission without acknowledgement
The microprocessor can use a simpler transmission, if it avoids detection of the
acknowledgement from the audio processor. It simply waits one clock pulse without
checking the slave acknowledgment, and sends the new data.
This approach of course is less protected from errors, increases the possibility of
interference, and decreases the immunity to noise.
2
C BUS interface
Figure
Figure 4.
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up
3., the data on the SDA line must be stable during the high period of the
a start condition is a HIGH to LOW transition of the SDA line while
Figure
5.). The peripheral (audioprocessor) that
TDA7348