ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 42

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
selector (that is, the 18:2 multiplexer) allows each serial output
port to clock from any available clock domain. In master mode,
the clock domain selector is bypassed, and the assignments
described in Table 28 are used.
Table 28. Output Clock Domain Assignments in Master Mode
Data Pin
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
The maximum number of audio channels that can be output
from SigmaDSP is 24. The serial output ports must be set in a
way that respects this (for example, two TDM16 streams is not a
valid entry).
All data is processed in twos complement, MSB-first format,
and the left channel always precedes the right channel.
INPUT PORTS
TO SERIAL
Clock Pins
LRCLK9, BCLK9
LRCLK10, BCLK10
LRCLK11, BCLK11
LRCLK3, BCLK3
LRCLK4, BCLK4
LRCLK5, BCLK5
LRCLK6, BCLK6
LRCLK7, BCLK7
LRCLK8, BCLK8
MULTIPLEXERS
CLOCK PAD
3 TO 8
(×6)
4:2
2
Figure 33. Output Serial Port Clock Multiplexing
4:2
2
Rev. C | Page 42 of 92
CLOCK DOMAINS
CLOCK DOMAIN
INPUT/OUTPUT
4:2
ASSIGNABLE
SELECTOR
2
3 TO 8
(×6)
4:2
SERIAL OUTPUT PORT MODES AND SETTINGS
Each of the nine serial output ports is controlled by setting an
individual 2-byte word in the serial output mode register for
each port (see Table 29 for the register addresses). Each serial
data signal can be set to use any of the nine clock domains
(slave mode) or an internally generated LRCLK signal at
f
on reset is set to TDM2, I
polarity slave mode using a 50% duty cycle LRCLK clock signal
(as opposed to a synchronization pulse). This configuration
corresponds to a setting of 0x3C00. The serial data uses its
corresponding clock domain (for example, SDATA3 uses
LRCLK3 and BCLK3).
Restrictions
When the device is in MOST mode, the MSB position of the
serial data is delayed by one bit clock from the start of the frame
(I
When the device is in MSB delay-by-12 mode, the serial data
can be 16 or 20 bits wide (not 24 bits). When the device is in
MSB delay-by-16 mode, the serial data can only be 16 bits wide.
For information on TDM capabilities, refer to Table 18.
2
S,NORMAL
2
S position) and the data width is restricted to 16 bits.
3
4:2
, f
4
2
S,DUAL
5
OUTPUT
SERIAL
PORTS
6
18:2
(×9)
(×9)
, or f
4:2
7
2
CLOCK DOMAINS
S,QUAD
8
DEDICATED
9 TO 11
OUTPUT
9
2
(×3)
. The default value for each serial port
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
2
10 11
S, 24-bit, negative LRCLK and BCLK
2
2