ADP5042 Analog Devices, ADP5042 Datasheet - Page 18
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ADP5042
Manufacturer Part Number
ADP5042
Description
Micro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
Manufacturer
Analog Devices
Datasheet
1.ADP5042.pdf
(32 pages)
ADP5042
THEORY OF OPERATION
POWER MANAGEMENT UNIT
The ADP5042 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc convertor, two low
dropout linear regulators (LDOs), and a supervisory circuit, with
dual watchdog, for processor control. The regulators are activated
by a logic level high applied to the respective EN pin. The EN1
controls the buck regulator, the EN2 controls LDO1, and the
EN3 controls LDO2. The ADP5042 has factory programmed
output voltages and reset voltage threshold. Other features
available in this device are the mode pin to control the buck
switching operation, a status pin informing the external processor
which watchdog caused a reset and push-button reset input.
When a regulator is turned on, the output voltage is controlled
through a soft start circuit to avoid a large inrush current due to
the discharged output capacitors.
MODE
PGND
AVIN
VIN1
EN1
EN2
EN3
SW
POFF
VDDA
OPMODE_FUSES
AND MODE
CONTROL
ADP5042
ENABLE
SEL
ANTISHOOT
THROUGH
DRIVER
PWM
COMP
I
LOW
CURRENT
LIMIT
AND
MODE
ENBK
ENLDO1
ENLDO2
VDDA
CONTROL
BUCK1
PWM/
GM ERROR
PSM
VIN2
AMP
SOFT START
UNDERVOLTAGE
OSCILLATOR
SHUTDOWN
LOCK OUT
THERMAL
COMP
SYSTEM
ENBK
PSM
CONTROL
Figure 56. Functional Block Diagram
LDO1
Rev. A | Page 18 of 32
60Ω
VOUT1
52kΩ
AGND VOUT2 VIN3
VDDA
R1
R2
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition is a function of
the current load and the output capacitor value. This operating
mode reduces the switching and quiescent current losses.
VDDA
MR
R0
A
B
C
D
WMOD
VDDA
Y
200kΩ
DEBOUNCE
ENWD1
R1
500Ω
V
REF
DETECTOR1
WATCHDOG
CONTROL
LDO2
WDI1
ENLDO1
WATCHDOG
GENERATOR
MONITOR
RESET
STATUS
ENLDO2
40kΩ
DETECTOR2
WATCHDOG
WDI2
R3
R4
500Ω
ENWD2
POFF
Data Sheet
VOUT3
WSTAT
nRSTO