ADUC7028 Analog Devices, ADUC7028 Datasheet - Page 51

• Manufacturer Part Number: ADUC7028
• Manufacturer: Analog Devices

Specifications of ADUC7028

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Flash (kbytes): 62Bytes
• Sram (bytes): 8192Bytes
• Gpio Pins: 40
• Adc # Channels: 8

Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
Table 44. REMAP Register
Name
REMAP
1
Table 45. REMAP MMR Bit Designations
Bit
4
3
2:1
0
Depends on the model.
Name
Remap
Address
0xFFFF0220
Description
Read-only bit. Indicates the size of the Flash/EE
memory available. If this bit is set, only 32 kB of
Flash/EE memory is available.
Read-only bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
Reserved.
Remap bit. Set by user to remap the SRAM to
Address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
Address 0x00000000.
Default Value
0xXX
1
Access
R/W
Rev. D | Page 51 of 96
Table 46. RSTSTA Register
Name
RSTSTA
Table 47. RSTSTA MMR Bit Designations
Bit
7:3
2
1
0
RSTCLR Table 48. Register
Name
RSTCLR
Note that to clear the RSTSTA register, the user must write 0x07
to the RSTCLR register.
ADuC7019/20/21/22/24/25/26/27/28/29
Description
Reserved.
Software reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog timeout. Set automatically when a watchdog
timeout occurs. Cleared by setting the corresponding
bit in RSTCLR.
Power-on reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit
in RSTCLR.
Address
0xFFFF0230
Address
0xFFFF0234
Default Value
0x01
Default Value
0x00
Access
R/W
Access
W