ADUC814 Analog Devices, ADUC814 Datasheet - Page 22

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

ADuC814
SFR INTERFACE TO ADC BLOCK
The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode
of operation.
ADCCON1 (ADC CONTROL SFR 1)
The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed
below.
SFR Address
SFR Power-on Default
Bit Addressable
Table 6. ADCCON1 SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
MODE
Name
MODE
EXT_REF
CK1
CK0
AQ1
AQ0
T2C
EXC
EXT_REF
Description
Mode Bit.
This bit selects the operating mode of the ADC.
Set to 1 by the user to power on the ADC.
Set to 0 by the user to power down the ADC.
External Reference Select Bit.
This bit selects which reference the ADC uses when performing a conversion.
Set to 1 by the user to switch in an external reference.
Set to 0 by the user to switch in the on-chip band gap reference.
ADC Clock Divide Bits.
CK1 and CK0 combine to select the divide ratio for the PLL master clock used to generate the ADC clock. To ensure
correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to 4.5 MHz and below. The
divider ratio is selected as follows:
CK1
0
0
1
1
The ADC Acquisition Time Select Bits.
AQ1 and AQ0 combine to select the number of ADC clocks required for the input track-and-hold amplifier to
acquire the input signal. The acquisition time is selected as follows:
AQ1
0
0
1
1
The Timer2 Conversion Bit.
T2C is set to enable the Timer2 overflow bit to be used as the ADC convert start trigger input.
The External Trigger Enable Bit.
EXC is set to allow the external CONVST pin be used as the active low convert start trigger input. When enabled, a
rising edge on this input pin trigger a conversion. This pin should remain low for a minimum pulse width of
100 nsec at the required sample rate.
EFH
00H
No
CK0
0
1
0
1
AQ0
0
1
0
1
CK1
8
4
16
32
No. ADC Clks
1
2
3
4
PLL Divider
CK0
Rev. A | Page 22 of 72
AQ1
AQ0
T2C
EXC