ADUC832 Analog Devices, ADUC832 Datasheet - Page 65

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

TIME INTERVAL COUNTER (TIC)
A time interval counter is provided on chip for counting longer
intervals than the standard 8051-compatible timers are capable of.
The TIC is capable of timeout intervals ranging from 1/128 second
to 255 hours. Furthermore, this counter is clocked by the exter-
nal 32.768 kHz crystal rather than the core clock, and has the
ability to remain active in power-down mode and time long
power-down intervals. This has obvious applications for remote
battery-powered sensors where regular widely spaced readings
are required. Note that instructions to the TIC SFRs are also
clocked at 32.768 kHz, and sufficient time must be allowed in
user code for these instructions to execute.
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
ITS0 and ITS1 bits in TIMECON, the selected time counter regis-
ter overflow clocks the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR, the
TII bit (TIMECON[2]) is set and generates an interrupt if
enabled. If the ADuC832 is in power-down mode, again with
the TIC interrupt enabled, the TII bit wakes up the device and
resumes code execution by vectoring directly to the TIC interrupt
service vector address at 0053H. The TIC-related SFRs are
described in the following sections. Note also that the timebase
SFRs can be written initially with the current time; the TIC can
then be controlled and accessed by user software. In effect, this
facilitates the implementation of a real-time clock. A block
diagram of the TIC is shown in Figure 65.
Table 33. TIMECON SFR Bit Designations
Bit
[7]
[6]
[5:4]
[3]
[2]
[1]
[0]
Name
Reserved
TFH
ITS[1:0]
STI
TII
TIEN
TCEN
Description
Reserved for future use.
Twenty-four hour select bit. Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to
enable the hour counter to count from 0 to 255.
Interval timebase selection bits. Written by user to determine the interval counter update rate.
ITS1
0
0
1
1
Single-time interval bit. Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit. Cleared
by the user to allow the interval counter to be automatically reloaded and starts counting again at each interval timeout.
TIC interrupt bit. Set when the 8-bit interval counter matches the value in the INTVAL SFR. Cleared by user software.
Time interval enable bit. Set by the user to enable the 8-bit time interval counter. Cleared by the user to disable the
interval counter.
Time clock enable bit. Set by the user to enable the time clock to the time interval counters. Cleared by the user to
disable the clock to the time interval counters and to reset the time interval SFRs to the last value written to them by the
user. The time registers (HTHSEC, SEC, MIN, and hour) can be written while TCEN is low.
ITS0
0
1
0
1
Rev. A | Page 65 of 92
Interval Timebase
1/128 second
Seconds
Minutes
Hours
TIMECON (TIC CONTROL REGISTER)
SFR Address:
Power-On Default Value:
Bit Addressable:
TIME INTERVAL COUNTER INTERRUPT
TCEN
32.768kHz EXTERNAL CRYSTAL
INTERVAL TIMEOUT
HUNDREDTHS COUNTER
SECOND COUNTER
MINUTE COUNTER
Figure 65. TIC, Simplified Block Diagram
HOUR COUNTER
PRESCALER
HOUR
8-BIT
HTHSEC
SEC
MIN
A1H
00H
No
INTERVAL COUNTER
COUNT = INTVAL
TIMER INTVAL
COMPARE
INTVAL
8-BIT
SELECTION
TIMEBASE
INTERVAL
ITS0, ITS1
MUX
ADuC832
TIEN