ADUC832 Analog Devices, ADUC832 Datasheet - Page 36

• Manufacturer Part Number: ADUC832
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 62kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC832

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC832
ADCCON1 (ADC Control SFR 1)
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
Table 16. ADCCON1 SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3:2]
[1]
[0]
Name
MD1
EXT_REF
CK1
CK0
AQ[1:0]
T2C
EXC
Description
The mode bit selects the active operating mode of the ADC. Set by the user to power up the ADC. Cleared by the user
to power down the ADC.
Set by the user to select an external reference. Cleared by the user to use the internal reference.
The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock used to generate the
ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock to ≤4.5 MHz. A
typical ADC conversion requires 17 ADC clocks. The divider ratio is selected as follows:
CK1
0
0
1
1
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier to acquire
the input signal. An acquisition of three or more ADC clocks is recommended; clocks are selected as follows:
AQ1
0
0
1
1
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit to be used as the ADC convert
start trigger input.
The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5/T1/CONVST to be used as the
active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the required
sample rate.
EFH
00H
No
CK0
0
1
0
1
AQ0
0
1
0
1
Rev. A | Page 36 of 92
MCLK Divider
8
4
16
32
Number of ADC Clocks
1
2
3
4
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes, and power-down modes as
detailed in Table 16.