ADUC842 Analog Devices, ADUC842 Datasheet - Page 73

• Manufacturer Part Number: ADUC842
• Description: Precision Analog Microcontroller: 16MIPS 8052 Flash MCU + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC842

• Mcu Core: 8052
• Mcu Speed (mips): 16
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

If access to more than 64 kBytes of RAM is desired, a feature
unique to the ADuC841/ADuC842/ADuC843 allows address-
ing up to 16 MBytes of external RAM simply by adding an
additional latch as illustrated in Figure 79.
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by a pulse of ALE prior to data
being placed on the bus by the ADuC841/ADuC842/ADuC843
(write operation) or by the SRAM (read operation). Port 2 (P2)
provides the data pointer page byte (DPP) to be latched by ALE,
followed by the data pointer high byte (DPH). If no latch is
connected to P2, DPP is ignored by the SRAM, and the 8051
standard of 64 kBytes external data memory access is maintained.
Power Supplies
The operational power supply voltage of the parts depends on
whether the part is the 3 V version or the 5 V version. The
specifications are given for power supplies within 2.7 V to 3.6 V
or ±5% of the nominal 5 V level.
Note that Figure 80 and Figure 81 refer to the PQFP package.
For the CSP package, connect the extra DV
and AGND in the same manner. Also, the paddle on the bottom
of the package should be soldered to a metal plate to provide
mechanical stability. This metal plate should not be connected
to ground.
Separate analog and digital power supply pins (AV
respectively) allow AV
digital signals that are often present on the system DV
However, though you can power AV
separate supplies if desired, you must ensure that they remain
within ±0.3 V of one another at all times to avoid damaging the
chip (as per the Absolute Maximum Ratings section). Therefore,
it is recommended that unless AV
directly together, back-to-back Schottky diodes should be con-
nected between them, as shown in Figure 80.
Figure 79. External Data Memory Interface (16 MBytes Address Space)
ADuC841/
ADuC842/
ADuC843
ALE
WR
RD
P0
P2
DD
to be kept relatively free of the noisy
LATCH
LATCH
DD
DD
and DV
and DV
D0–D7
(DATA)
A0–A7
A8–A15
A16–A23
OE
WE
DD
DD
, DGND, AV
DD
SRAM
are connected
from two
DD
and DV
DD
line.
DD
,
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DD
,
As an alternative to providing two separate power supplies, the
user can help keep AV
and/or ferrite bead between it and DV
AV
shown in Figure 81. With this configuration, other analog
circuitry (such as op amps and voltage reference) can be powered
from the AV
include back-to-back Schottky diodes between AV
to protect them from power-up and power-down transient
conditions that could momentarily separate the two supply voltages.
Notice that in both Figure 80 and Figure 81, a large value
(10 µF) reservoir capacitor sits on DV
capacitor sits on AV
tors are located at each V
design practice, be sure to include all of these capacitors, and
ensure the smaller capacitors are close to each AV
trace lengths as short as possible. Connect the ground terminal
of each of these capacitors directly to the underlying ground
plane. Finally, note that at all times, the analog and digital ground
pins on the part must be referenced to the same system ground
reference point.
DD
separately to ground. An example of this configuration is
DIGITAL SUPPLY
DIGITAL SUPPLY
+
–
0.1µF
+
–
0.1µF
DD
Figure 81. External Single-Supply Connections
Figure 80. External Dual-Supply Connections
supply line as well. The user will still want to
10µF
10µF
DD
ADuC841/ADuC842/ADuC843
. Also, local small-value (0.1 µF) capaci-
DD
quiet by placing a small series resistor
DD
pin of the chip. As per standard
DV
DGND
DV
DGND
BEAD
DD
DD
ADuC841/
ADuC842/
ADuC843
ADuC841/
ADuC842/
ADuC843
1.6Ω
DD
DD
AGND
AGND
AV
AV
, and then decoupling
and a separate 10 µF
ANALOG SUPPLY
DD
10µF
DD
10µF
0.1µF
0.1µF
DD
DD
+
–
pin with
and DV
DD