ADUC842 Analog Devices, ADUC842 Datasheet
ADUC842
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ADUC842 Summary of contents
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... The ADuC841 and ADuC842 are identical with the exception of the clock oscillator circuit; the ADuC841 is clocked directly from an external crystal MHz whereas the ADuC842 uses a 32 kHz crystal with an on-chip PLL generating a programmable core clock up to 16.78 MHz. ...
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... ADuC841/ADuC842/ADuC843 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configurations and Functional Descriptions ........................ 9 Terminology .................................................................................... 11 ADC Specifications .................................................................... 11 DAC Specifications..................................................................... 11 Typical Performance Characteristics ........................................... 12 Functional Description .................................................................. 16 8052 Instruction Set ................................................................... 16 Other Single-Cycle Core Features ............................................ 18 Memory Organization ............................................................... 19 Special Function Registers (SFRs)............................................ 20 Accumulator SFR (ACC)........................................................... 21 Special Function Register Banks .............................................. 22 ADC Circuit Information ...
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... ANALOG INPUT Input Voltage Range Leakage Current Input Capacitance 9 TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy DAC CHANNEL SPECIFICATIONS Internal Buffer Enabled ADuC841/ADuC842 Only 10 DC ACCURACY Resolution Relative Accuracy 11 Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ANALOG OUTPUTS ...
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... ADuC841/ADuC842/ADuC843 Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy 12, 13 DAC CHANNEL SPECIFICATIONS Internal Buffer Disabled ADuC841/ADuC842 Only 10 DC ACCURACY Resolution Relative Accuracy 11 Differential Nonlinearity Offset Error Gain Error 4 Gain Error Mismatch ANALOG OUTPUTS Voltage Range_0 REFERENCE INPUT/OUTPUT REFERENCE OUTPUT ...
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... Rev Page ADuC841/ADuC842/ADuC843 Test Conditions/Comments ADuC842/ADuC843 Only ADuC841 Only µA SOURCE µA SOURCE I = 1.6 mA SINK I = 1.6 mA ...
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... Oscillator Off / TIMECON µA typ µA typ Core CLK = any frequency ADuC841 Only mA max TIMECON µA max Core CLK = any frequency µA typ ADuC842/ADuC843 Only Oscillator On µA typ min MCLK Divider = 32 mA max MCLK Divider = 2 µA typ ...
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... Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), core executing internal software loop. Idle Mode: Reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), PCON core execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, all Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON (ADuC842/ADuC843), PCON ...
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... USER XRAM MCU CORE 2 × DATA POINTERS 11-BIT STACK POINTER DOWNLOADER DEBUGGER ASYNCHRONOUS UART SERIAL PORT POR TIMER (UART) No DACs on ADuC843, PLL on ADuC842/ADuC843 Only. Rev Page 12-BIT VOLTAGE DAC0 OUTPUT DAC 12-BIT DAC VOLTAGE DAC1 CONTROL OUTPUT DAC 16-BIT Σ ...
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... C Compatible, or SPI Data Input/Output Pin Compatible or for SPI Serial Interface Clock. Rev Page ADuC841/ADuC842/ADuC843 1 2 PIN 1 IDENTIFIER ADuC841/ADuC842/ADuC843 6 7 56-LEAD CSP 8 TOP VIEW (Not to Scale Figure 4. 56-Lead CSP pin should be used instead. REF P2 ...
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... ADuC841/ADuC842/ADuC843 Mnemonic Type Function P3.0–P3.7 I/O Port bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low source current because of the internal pull-up resistors. Port 3 pins also contain various secondary functions, which are described below ...
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... The amount of time it takes for the output to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Impulse The amount of charge injected into the analog output when the inputs change state specified as the area of the glitch in nV-sec. /2), excluding dc. S Rev Page ADuC841/ADuC842/ADuC843 ...
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... ADuC841/ADuC842/ADuC843 TYPICAL PERFORMANCE CHARACTERISTICS The typical performance plots presented in this section illustrate typical performance of the ADuC841/ADuC842/ ADuC843 under various operating conditions. Figure 5 and Figure 6 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 and 3 V supplies, respectively. The ADC is using its internal reference (2.5 V) and is operating at a sampling rate of 152 kHz ...
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... DD DD 0.8 = 152kHz 0.4 0.6 0.4 0.2 0 –0.2 –0.2 –0.4 –0.6 –0.4 –0.8 –0.6 –1.0 5 REF DD Rev Page ADuC841/ADuC842/ADuC843 AV / 152kHz S WCP INL WCN INL 0.5 1.0 1.5 2.0 2.5 3.0 EXTERNAL REFERENCE (V) Figure 10. Typical Worst-Case INL Error vs REF AV / 152kHz S 0 511 1023 1535 ...
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... ADuC841/ADuC842/ADuC843 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 13. Typical Worst-Case DNL Error vs. V 0.7 0.5 0.3 0.1 –0.1 –0.3 –0.5 –0.7 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 14. Typical Worst-Case DNL Error vs. V 10000 8000 6000 4000 2000 0 817 818 819 CODE Figure 15. Code Histogram Plot, V 10000 0 152kHz S 0 ...
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... DACs, a dual output 16-bit PWM, a watchdog timer, a time interval counter, three timers/counters, and three serial I/O 2 ports (SPI and UART). On the ADuC812 and the ADuC832, the I share some of the same pins. For backwards compatibility, this is also the case for the ADuC841/ADuC842/ADuC843. – ...
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... Table 4 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting MIPS peak performance when operating at PLLCON = 00H on the ADuC842/ADuC843. On the ADuC841, 20 MIPS peak performance is possible with a 20 MHz external crystal. Table 4. Instructions ...
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... AND direct bit and carry ANL C,/bit AND direct bit inverse to carry ORL C,bit OR direct bit and carry ORL C,/bit OR direct bit inverse to carry MOV C,bit Move direct bit to carry MOV bit,C Move carry to direct bit ADuC841/ADuC842/ADuC843 Bytes ...
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... The output on the ALE pin on a standard 8052 part is a clock at 1/6th of the core operating frequency. On the ADuC841/ ADuC842/ADuC843 the ALE pin operates as follows. For a single machine cycle instruction,ALE is high for the first half of the machine cycle and low for the second half. The ALE output is at the core operating frequency ...
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... MEMORY ORGANIZATION The ADuC841/ADuC842/ADuC843 each contain four different memory blocks: • kBytes of on-chip Flash/EE program memory • 4 kBytes of on-chip Flash/EE data memory • 256 bytes of general-purpose RAM • 2 kBytes of internal XRAM Flash/EE Program Memory The parts provide kBytes of Flash/EE program mem- ory to run user code ...
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... Figure 24. Extended Stack Pointer Operation External Data Memory (External XRAM) Just like a standard 8051 compatible core, the ADuC841/ ADuC842/ADuC843 can access external data memory by using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. ...
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... DPTR instructions automatically carry over to DPP three independent 8-bit registers (DPP, DPH, DPL). The parts support dual data pointers. Refer to the Dual Data Pointer section. ADuC841/ADuC842/ADuC843 Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU, as detailed in Table 5 ...
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... ADuC841/ADuC842/ADuC843 SPECIAL FUNCTION REGISTER BANKS All registers except the program counter and the four general- purpose register banks reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers, which provide an interface between the CPU and other on-chip peripherals. Figure 27 shows a full SFR memory map and SFR contents on reset ...
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... RAM space without any interaction from the MCU core. This automatic capture facility can extend through a 16 MByte external data memory space. The ADuC841/ADuC842/ADuC843 are shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power-up, ensuring optimum ADC performance ...
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... Cleared by the user to use the internal reference. 5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock (ADuC842/ADuC843) or the external crystal (ADuC841) used to generate the ADC clock. To ensure correct ADC operation, the divider ratio 4 CK0 must be chosen to reduce the ADC clock to 8 ...
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... DAC0 Only use with internal DAC output buffer on DAC1 Only use with internal DAC output buffer on AGND REF 1 1 DMA STOP Place in XRAM location to finish DMA sequence; refer to the ADC DMA Mode section. Rev Page ADuC841/ADuC842/ADuC843 ...
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... ADuC841/ADuC842/ADuC843 ADCCON3—(ADC Control SFR 3) The ADCCON3 register controls the operation of various calibration modes and also indicates the ADC busy status. SFR Address F5H SFR Power-On Default 00H Bit Addressable No Table 9. ADCCON3 SFR Bit Designations Bit No. Name Description 7 BUSY ADC Busy Status Bit. ...
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... Some single-supply rail-to-rail op amps that are useful for this purpose are described in Table 11. Check Analog Devices website www.analog.com instrumentation amps. Rev Page ADuC841/ADuC842/ADuC843 ADuC841/ ADuC842/ ADuC843 10Ω AIN0 0.1µ F Figure 31. Buffering Analog Inputs or below ground Error from 1 µ ...
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... Rev Page pin as shown in Figure 33. Bit 6 of the REF . In situations where analog DD pin directly Operation of the ADC or DACs REF DD ADuC841/ADuC842/ADuC843 V DD EXTERNAL 51 Ω 2.5V VOLTAGE BAND GAP REFERENCE REFERENCE 0 = INTERNAL ...
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... ADC DMA Mode The on-chip ADC has been designed to run at a maximum conversion speed of 2.38 µs (420 kHz sampling rate). When converting at this rate, the ADuC841/ADuC842/ADuC843 MicroConverter has 2 µs to read the ADC result and to store the result in memory for further postprocessing; otherwise the next ADC sample could be lost ...
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... ADC Offset and Gain Calibration Coefficients The ADuC841/ADuC842/ADuC843 have two ADC calibration coefficients, one for offset calibration and one for gain calibra- tion. Both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the special function register (SFR) area ...
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... REF mability, high density, and low cost. Incorporated in the parts, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. Flash/EE Memory and the ADuC841/ADuC842/ADuC843 ( ) + 16 T ...
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... Flash/EE program memory while the device is in-circuit in its target application hardware serial download executable is provided as part of the ADuC841/ADuC842 QuickStart development system. The serial download protocol is detailed in MicroConverter Application Note uC004. Parallel Programming Parallel programming mode is fully compatible with conven- tional third party flash or EEPROM device programmers ...
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... ULOAD MEMORY Figure 40. Flash/EE Program Memory Map in ULOAD Mode Flash/EE Program Memory Security The ADuC841/ADuC842/ADuC843 facilitate three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial download protocol as described in Application Note uC004 or via parallel programming ...
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... ADuC841/ADuC842/ADuC843 USING FLASH/EE DATA MEMORY The 4 kBytes of Flash/EE data memory are configured as 1024 pages, each of 4 bytes. As with the other ADuC841/ADuC842/ ADuC843 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) is used to hold the four bytes of data at each page ...
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... Flash/EE array. This command coded in 8051 assembly would appear as MOV ECON,#06H ; Erase all Command ; 2 ms Duration ADuC841/ADuC842/ADuC843 Flash/EE Memory Timing Typical program and erase times for the parts are as follows: Normal Mode (operating on Flash/EE data memory) READPAGE (4 bytes) WRITEPAGE (4 bytes) ...
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... The CFG842 SFR contains the necessary bits to configure the internal XRAM, external clock select, PWM output selection, DAC buffer, and the extended SP for both the ADuC842 and the ADuC843. By default, it configures the user into 8051 mode, i.e., extended SP is disabled and internal XRAM is disabled. On the ADuC841, this register is the CFG841 register and is described on the next page ...
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... Note that the Flash/EE controller bits EPM2, EPM1, EPM0 are set to their correct values depending on the crystal frequency at power-up. The user should not modify these bits so all instructions to the CFG841 register should use the ORL, XRL, or ANL instructions. Value of 10H is for 11.0592 MHz crystal. /Divide Factor = 32 kHz + 50%. OSC EPM0 Divide Factor 128 1 256 0 512 1 1024 Rev Page ADuC841/ADuC842/ADuC843 ...
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... A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC841/ADuC842 incorporate two 12-bit voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges (the internal band gap 2 ...
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... Figure 44. Source and Sink Current Capability with < the lower Figure 45. Source and Sink Current Capability with V Rev Page ADuC841/ADuC842/ADuC843 000H DAC LOADED WITH 0FFFH DAC LOADED WITH 0000H SOURCE/SINK CURRENT (mA) REF DAC LOADED WITH 0FFFH DAC LOADED WITH 0000H ...
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... DAC output. Assuming this resistor is in place, the DAC outputs remain at ground potential whenever the DAC is disabled. range. REF Rev Page DAC0 ADuC841/ ADuC842 DAC1 Figure 46. Buffering the DAC Outputs ...
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... ON-CHIP PLL The ADuC842 and ADuC843 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of this to provide a stable 16.78 MHz clock for the system. The ADuC841 operates directly from an external crystal. The core can operate at this frequency or at binary submultiples allow power saving in cases where maximum core performance is not required ...
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... ADuC841/ADuC842/ADuC843 PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC841/ADuC842/ADuC843 is a highly flexible PWM offering programmable resolution and an input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be config- ured as a ∑-∆ DAC with bits of resolution. A block diagram of the PWM is shown in Figure 47. Note the PWM clock’ ...
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... PWM1H/L, PWM1 (P2.7) goes low and remains low until the P2.7 PWM counter rolls over. In this mode, both PWM outputs are synchronized, i.e., once the PWM counter rolls over to 0, both PWM0 (P2.6) and PWM1 go high. Rev Page ADuC841/ADuC842/ADuC843 PWM1L PWM COUNTER PWM0H PWM0L PWM1H 0 P2 ...
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... ADuC841/ADuC842/ADuC843 Mode 4: Dual NRZ 16-Bit ∑-∆ DAC Mode 4 provides a high speed PWM output similar to that of a -∆ DAC. Typically, this mode is used with the PWM clock ∑ equal to 16.777216 MHz. In this mode, P2.6 and P2.7 are updated every PWM clock ( the case of 16 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for (65536 – ...
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... SERIAL PERIPHERAL INTERFACE (SPI) The ADuC841/ADuC842/ADuC843 integrate a complete hard- ware serial peripheral interface on-chip. SPI is an industry- standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. Note that the SPI pins are shared with the I pins ...
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... ADuC841/ADuC842/ADuC843 SPICON SPI Control Register SFR Address F8H Power-On Default 04H Bit Addressable Yes Table 18. SPICON SFR Bit Designations Bit No. Name Description 7 ISPI SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. ...
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... Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table 18, the ADuC841/ADuC842/ADuC843 SPI interface transmits or receives data in a number of possible modes. Figure 54 shows all possible SPI configurations for the parts, and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication ...
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... ADuC841/ADuC842/ADuC843 COMPATIBLE INTERFACE The ADuC841/ADuC842/ADuC843 support a fully licensed serial interface. The I C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin, and SCLOCK is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. To ...
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... C interface. Accessing I2CDAT automatically clears any pending interface are address, single master/slave relationships can exist at all times even in a multislave environment. • Ability to respond to four separate addresses when operating in slave mode. Rev Page ADuC841/ADuC842/ADuC843 2 C standard 7-bit address interrupt and ...
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... SLAVE 1 SLAVE 2 2 Figure 55. Typical I C System Software Master Mode The ADuC841/ADuC842/ADuC843 can be used devices by configuring the I C peripheral in master mode and writing software to output the data bit by bit. This is referred software master. Master mode is enabled by setting the I2CM bit in the I2CCON register ...
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... DUAL DATA POINTER The ADuC841/ADuC842/ADuC843 incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes some useful features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle ...
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... ADuC841/ADuC842/ADuC843 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the DV supply on the ADuC841/ADuC842/ DD ADuC843. It indicates when any of the supply pins drops below one of two user selectable voltage trip points, 2.93 V and 3.08 V. For correct operation of the power supply monitor function, AV must be equal to or greater than 2 ...
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... WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC841/ ADuC842/ADuC843 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR. When enabled, the ...
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... A block diagram of the TIC is shown in Figure 56. The TIC is clocked directly from a 32 kHz external crystal on the ADuC842/ADuC843 and by the internal 32 kHz ±10% R/C oscillator on the ADuC841. Due to this, instructions that access the TIC registers will also be clocked at this speed. The user should ensure that there is sufficient time between instructions to these registers to allow them to execute correctly ...
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... Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is low. Interval Timebase 1/128 Second Seconds Minutes Hours Rev Page ADuC841/ADuC842/ADuC843 ...
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... ADuC841/ADuC842/ADuC843 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. SFR Address ...
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... These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Parallel I/O The ADuC841/ADuC842/ADuC843 use four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device ...
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... ADuC841/ADuC842/ADuC843 In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 60) and, in that state, can be used as inputs. As inputs, Port 2 pins being pulled externally low source current because of the internal pull-up resistors. Port 2 pins with 0s written to them drive a logic low output voltage (V sinking 1 ...
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... Logic 0. Reading the latch rather Q 4 than the pin returns the correct value Mode Rev Page ADuC841/ADuC842/ADuC843 Description Logical AND, e.g., ANL P1, A (Logical OR, e.g., ORL P2, A (Logical EX-OR, e.g., XRL P3, A Jump if Bit = 1 and clear bit, e.g., JBC P1.1, LABEL Complement bit, e ...
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... ADuC841/ADuC842/ADuC843 Timers/Counters The ADuC841/ADuC842/ADuC843 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx ( and 2). All three can be configured to operate either as timers or as event counters ...
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... Timer/Counter 0 and 1 Data Registers Each timer consists of two 8-bit registers. These can be used as independent registers or combined into a single 16-bit register depending on the timer mode configuration. ADuC841/ADuC842/ADuC843 TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte ...
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... ADuC841/ADuC842/ADuC843 TIMER/COUNTER 0 AND 1 OPERATING MODES The following sections describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, assume that these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter. Figure 66 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single-cycle core ...
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... These are used as both timer data registers and as timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH, respectively. RCAP2H and RCAP2L Timer 2, capture/reload byte and low byte. SFR Address = CBH, CAH, respectively. ADuC841/ADuC842/ADuC843 Rev Page ...
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... ADuC841/ADuC842/ADuC843 TIMER/COUNTER OPERATING MODES The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR, as shown in Table 31. Table 31. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 16-Bit Autoreload Mode Autoreload mode has two options that are selected by Bit EXEN2 in T2CON ...
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... Selected Operating Mode. Mode 0: Shift Register, fixed baud rate (Core_Clk/2). Mode 1: 8-bit UART, variable baud rate. Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16). Mode 3: 9-bit UART, variable baud rate. Rev Page ADuC841/ADuC842/ADuC843 Serial Port Control Register 98H 00H Yes ...
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... ADuC841/ADuC842/ADuC843 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD out- puts the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. ...
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... TIMER 2 OVERFLOW TL2 TH2 (8 BITS) (8 BITS TR2 RELOAD RCAP2H RCAP2L TIMER 2 EXF 2 INTERRUPT CONTROL EXEN2 Figure 73. Timer 2, UART Baud Rates Rev Page ADuC841/ADuC842/ADuC843 /32) × (Core Clock/ [256 − TH1]) TIMER 1 OVERFLOW SMOD 1 0 RCLK RX 16 CLOCK 1 0 TCLK TX ...
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... ADuC841/ADuC842/ADuC843 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the part has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates ...
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... Rev Page ADuC841/ADuC842/ADuC843 T3FD % Error 09H 0.25 09H 0.25 09H 0.25 09H 0.25 09H 0.25 09H 0.25 09H 0.25 09H 0.25 2DH 0.2 2DH 0.2 2DH 0.2 2DH 0.2 2DH 0.2 2DH 0.2 2DH 0.2 2DH 0.2 2DH ...
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... ADuC841/ADuC842/ADuC843 INTERRUPT SYSTEM The ADuC841/ADuC842/ADuC843 provide a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE Interrupt Enable Register IP Interrupt Priority Register Secondary Interrupt Enable Register IEIP2 IE Interrupt Enable Register ...
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... The interrupt vector addresses are shown in Table 39. Table 39. Interrupt Vector Addresses Source IE0 TF0 IE1 TF1 TF2 + EXF2 ADCI ISPI/I2CI PSMI TII WDS 2 C Interrupt. Rev Page ADuC841/ADuC842/ADuC843 Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 0053H 005BH ...
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... SOURCE XTAL2 Figure 76. Connecting an External Clock Source (ADuC841) Figure 77. Connecting an External Clock Source (ADuC842/ADuC843) Whether using the internal PLL or an external clock source, the parts’ specified operational clock speed range is 400 kHz to 16.777216 MHz, (20 MHz, ADuC841). The core itself is static, and functions all the way down to dc ...
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... It emits the low byte of the data pointer (DPL address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC841/ADuC842/ADuC843 (write operation the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP latched by ALE, followed by the data pointer high byte (DPH) ...
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... INT0 pin must not be driven low during or within two machine cycles of the instruction that initiates power-down mode. Note that the INT0 power-down interrupt enable bit (INT0PD) in the PCON SFR must be set to allow this mode of operation. Power-On Reset (POR) An internal POR is implemented on the ADuC841/ADuC842/ ADuC843 Part For DV DD ...
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... Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC841/ ADuC842/ADuC843 based designs to achieve optimum performance from the ADC and the DACs. Although the parts have separate pins for analog and digital ground (AGND and ...
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... In-Circuit Serial Download Access Nearly all ADuC841/ADuC842/ADuC843 designs want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC841/ADuC842/ ADuC843’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configura- tion of an RS-232 connection is illustrated in Figure 85 with a simple ADM202 based circuit ...
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... Single-Pin Emulation Mode Also built into the part is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC841/ ADuC842/ADuC843 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier ...
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... LOAD 4 ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 2 ...
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... LLWL RLRH t AVWL t RLDV t LLAX t RHDX t RLAZ A0 A7 (OUT) DATA (IN) t AVDV A16 A23 A8 A15 Figure 88. External Data Memory Read Cycle Rev Page ADuC841/ADuC842/ADuC843 8 MHz Core Clock Min Max Unit 125 ns 120 ns 290 ns 100 625 ns 350 ns 470 ns 255 ...
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... ADuC841/ADuC842/ADuC843 Parameter EXTERNAL DATA MEMORY WRITE CYCLE t WR Pulse Width WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low Low LLWL t Address Valid Low AVWL t Data Valid to WR Transition QVWX t Data Setup before WR ...
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... PSU SCLK (I) PS STOP START CONDITION CONDITION t SUP MSB LSB t DSU t DHD SHD 1 2 SUP 2 Figure 90 Compatible Interface Timing Rev Page ADuC841/ADuC842/ADuC843 Min Max 1.3 0.6 0.6 100 0.9 0.6 0.6 1.3 300 300 ACK MSB DHD RSU REPEATED ...
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... ADuC841/ADuC842/ADuC843 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge DHD ...
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... MSB IN MISO t DSU DAV MSB BITS 6–1 BITS 6–1 t DHD Figure 92. SPI Master Mode Timing (CPHA = 0) Rev Page ADuC841/ADuC842/ADuC843 Min Typ Max 476 476 50 150 100 100 LSB LSB IN ...
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... ADuC841/ADuC842/ADuC843 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... DOSS MISO MOSI MSB IN t DSU DAV BITS 6–1 MSB BITS 6–1 t DHD Figure 94. SPI Slave Mode Timing (CPHA = 0) Rev Page ADuC841/ADuC842/ADuC843 Min Typ Max 0 330 330 50 100 100 SFS ...
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... ADuC841/ADuC842/ADuC843 OUTLINE DIMENSIONS 2.10 2.00 1.95 VIEW A ROTATED 90° CCW PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 1.03 2.45 0.88 MAX 0. SEATING PLANE 7.80 REF VIEW A PIN 7° 0° 0.23 0.65 BSC 0.13 MIN 0.11 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 95. 52-Lead Plastic Quad Flatpack [MQFP] (S-52) Dimensions shown in millimeters 8.00 BSC SQ ...
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... EVAL-ADuC842QSP 5 1 The only difference between the ADuC842 and ADuC843 parts is the voltage output DACs on the ADuC842; thus the evaluation system for the ADuC842 is also suitable for the ADuC843. 2 The Quickstart Plus system can only be ordered directly from Accutron. It can be purchased from the website www.accutron.com. ...
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... ADuC841/ADuC842/ADuC843 Notes Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...