ADM1060 Analog Devices, ADM1060 Datasheet - Page 19

• Manufacturer Part Number: ADM1060
• Description: Multi Power Supply Sequencer & Supervisor
• Manufacturer: Analog Devices

Specifications of ADM1060

• # Supplies Monitored: 7
• Volt Monitoring Accuracy: 2.5%
• # Output Drivers: 9
• Fet Drive/enable Output: Both
• Package: 28 ld TSSOP

GENERAL-PURPOSE INPUTS (GPIs)
The ADM1060 has four general-purpose logic inputs (GPIs).
These are TTL/CMOS logic level compatible. Standard logic
signals can be applied to the pins: RESET from reset generators,
PWRGOOD signals, fault flags, manual resets, and so on. These
signals can be gated with the other inputs supervised by the
ADM1060 and used to control the status of the PDOs. The
inputs can be simply buffered, or a logic transition can be
detected and a pulse output generated. The width of this pulse is
programmable from 10 µs to a maximum of 10 ms. The
configuration of the GPIs is shown in the register and bit maps
below.
The GPIs also feature a glitch filter similar to that provided on
the SFDs. This enables the user to ignore spurious transitions
on the GPIs. For example, the glitch filter can be used to
Table 22. General-Purpose Inputs (GPIn) Registers
Hex Address
98
99
9A
9B
Table 23. GPInCFG Registers Bit Map (Power-On Default 0x00)
Bit
7
6
5
4–3
2–0
Name
Reserved
INVIN
INTYP
PULS1−0
GF2−GF0
Name
GPI4CFG
GPI3CFG
GPI2CFG
GPI1CFG
R/W
N/A
R/W
R/W
R/W
R/W
Description
Cannot Be Used
If High, Invert Input
Determines whether a Level or an Edge is Detected on
the Pin. If an edge is detected, a positive pulse of
programmable length is output.
Length of Pulse Output Once an Edge Has Been
Detected on Input
Length of Time for which the Input Is Ignored
Default Power-On Value
0x00
0x00
0x00
0x00
Rev. B | Page 19 of 52
Description
GPI4 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
GPI3 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
GPI2 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
GPI1 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
debounce a manual reset switch. The length of the glitch filter
can also be programmed.
LOGIC STATE OF THE GPIs AND OTHER LOGIC
INPUTS
Each of the GPIs can have a weak (10 µA) pull-down current
source. The current sources can be connected to the inputs by
progamming the relevant bit in the PDEN register. This enables
the user to control the condition of these inputs, pulling them to
GND even when they are unused or left floating.
Note that the same pull-down function is provided for the
SMBus address pins, A0 and A1, and for the WDI pin. A register
is used to program which of the inputs is connected to the cur-
rent sources.
INTYP
0
1
PULS1
0
0
1
1
GF2
0
0
0
0
1
1
1
1
Detect
Detect Level
Detect Edge
PULS0
0
1
0
1
GF1
0
0
1
1
0
0
1
1
Pulse Length Selected (µs)
10
100
1,000
10,000
GF0
0
1
0
1
0
1
0
1
Glitch Filter
Delay (µs)
0
5
10
20
30
50
75
100
ADM1060