ADM697 Analog Devices, ADM697 Datasheet - Page 4

• Manufacturer Part Number: ADM697
• Manufacturer: Analog Devices

Specifications of ADM697

• Product Description: µP Supv with CE Inputs, Adj Low Line V Monitor, Adj W-dog Timer, Low Line, Pwr Fail & W-dog Status
• Reset Threshold (v): 1.3,Adjustable
• Min Reset Timeout (ms): 35
• Reset Output-stage: Active-High/Push-Pull,Active-Low/Push-Pull
• Backup-battery Switch: No
• Chip Enable Gating: Yes
• Typ Watchdog Timeout (ms): 100,1600,adj.
• Package: DIP,SOIC
• Us Price 1000-4999: n/a
• Display In Ist: Yes
• Batt Source Sel Flg: Y
• Reset Threshold Summary: 1.3V (Adjustable)
• Min Positive Supply (v): +3V
• Batt-backup-flg: Yes

ADM696/ADM697
Mnemonic
V
V
V
GND
RESET
WDI
PFI
PFO
CE
CE
BATT ON
LOW LINE
RESET
OSC SEL
OSC IN
WDO
NC
LL
TEST
CC
BATT
OUT
IN
IN
OUT
ADM696
3
1
2
4
15
11
9
10
—
—
5
6
16
8
7
14
12
13
—
Pin No.
ADM697
3
—
—
5
15
11
9
10
13
12
—
6
16
8
7
14
2
4
1
Function
Power Supply Input +3 V to +5 V.
Backup Battery Input. Connect to Ground if a backup battery is not used.
Output Voltage, V
highest potential. V
V
0 V. Ground reference for all signals.
Logic Output. RESET goes low whenever LL
the V
RESET also goes low for 50 ms if the watchdog timer is enabled but not serviced within its
timeout period. The RESET pulse width can be adjusted as shown in Table I.
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V, PFO goes low. Connect PFI to GND or V
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and PFO goes low when V
V
Logic Input. The input to the CE gating circuit. Connect to GND or V
Logic Output. CE
is above 1.3 V. If LL
Logic Output. BATT ON goes high when V
It goes low when V
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
Logic Output. LOW LINE goes low when LL
LL
Logic Output. RESET is an active high output. It is the inverse of RESET.
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low,
the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 A internal pullup. See
Table I and Figure 4.
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog time-out period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods.
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog time-out period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
No Connect. It should be left open.
Voltage Sensing Input. The voltage on the low line input, LL
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a LOW LINE output signal. It also generates a
RESET/RESET output.
This is a special test pin using during device manufacture. It should be connected to GND.
CC
BATT
IN
if V
BATT
rises above 1.3 V.
.
OUT
PIN FUNCTION DESCRIPTION
input voltage. RESET remains low for 50 ms after LL
and V
OUT
CC
BATT
OUT
OUT
IN
or V
is a gated version of the CE
OUT
is below 1.3 V, CE
is internally switched to V
are not used.
can supply up to 100 mA to power CMOS RAM. Connect V
–4–
BATT
.
is internally switched to V
OUT
OUT
IN
IN
is forced high.
falls below 1.3 V or when V
is internally switched to the V
falls below 1.3 V. It returns high as soon as
CC
IN
. The output typically sinks 7 mA and
signal. CE
OUT
OUT
IN
depending on which is at the
when not used. See Figure 1.
OUT
, is compared with a 1.3 V
IN
goes above 1.3 V,
tracks CE
OUT
CC
if not used.
CC
IN
is below
BATT
falls below
when LL
input.
OUT
REV. 0
IN
to