ADM697 Analog Devices, ADM697 Datasheet - Page 10

• Manufacturer Part Number: ADM697
• Manufacturer: Analog Devices

Specifications of ADM697

• Product Description: µP Supv with CE Inputs, Adj Low Line V Monitor, Adj W-dog Timer, Low Line, Pwr Fail & W-dog Status
• Reset Threshold (v): 1.3,Adjustable
• Min Reset Timeout (ms): 35
• Reset Output-stage: Active-High/Push-Pull,Active-Low/Push-Pull
• Backup-battery Switch: No
• Chip Enable Gating: Yes
• Typ Watchdog Timeout (ms): 100,1600,adj.
• Package: DIP,SOIC
• Us Price 1000-4999: n/a
• Display In Ist: Yes
• Batt Source Sel Flg: Y
• Reset Threshold Summary: 1.3V (Adjustable)
• Min Positive Supply (v): +3V
• Batt-backup-flg: Yes

ADM696/ADM697
Replacing the Back-Up Battery
When changing the back-up battery with system power on, spu-
rious resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V
charge up the stray capacitance. If the voltage on V
within 50 mV of V
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following solu-
tions should be considered:
1. A capacitor from V
2. A resistor from V
TYPICAL APPLICATIONS
ADM696
Figure 18 shows the ADM696 in a typical power monitoring,
battery backup application. V
Under normal operating conditions with V
internally connected to V
decay and V
power for the CMOS RAM.
Power Fail RESET
The V
put, LL
1.3 V. RESET will remain low for 50 ms after LL
above 1.3 V. This allows for a power-on reset and prevents re-
peated toggling of RESET if the V
Resistors R3 and R4 should be chosen to give the desired V
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the P system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
capacitor is charging up to change the battery. The leakage
current will charge up the external capacitor towards the
V
the size of external capacitor and the voltage differential be-
tween the capacitor and the charging voltage supply.
The maximum leakage (charging) current is 1 A over tem-
perature and V
size should be chosen such that sufficient time is available to
make the battery replacement.
If a replacement time of 5 s is allowed and assuming a V
of 4.5 V and a V
on V
replacement.
Note that the resistor will discharge the battery slightly.
With a V
With a 3 V battery, this will draw around 700 nA. This will
be negligible in most cases.
CC
CC
IN
level. The time taken is related to the charging current,
BATT
power supply is also monitored by the Low Line In-
. A RESET pulse is generated when LL
OUT
CC
from rising to within 50 mV of V
C
supply of 4.5 V, a suitable resistor is 4.3 M .
EXT
will be switched to V
CC
DIFF
R = (V
= T
BATT
, a reset pulse is generated.
BATT
BATT
= V
REQD
C
t = C
of 3 V,
CC
to GND. This will prevent the voltage
EXT
CC
CC
. If a power failure occurs, V
to GND. This gives time while the
(1 A/(V
OUT
– 50 mV)/1 A
V
= 3.33 F
EXT
BATT
powers the CMOS RAM.
CC
V
. Therefore, the capacitor
BATT
power supply is unstable.
DIFF
CC
– V
/I
, thereby maintaining
CC
BATT
present, V
CC
BATT
))
IN
during battery
IN
BATT
falls below
returns
pin will
OUT
reaches
CC
will
CC
CC
is
–10–
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age V
RESET threshold so that there is sufficient time available to
complete the shutdown procedure before the processor is
RESET and power is lost.
Figure 18b shows a similar application for the ADM696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
INPUT
POWER
RESET
Figure 18a. ADM696 Typical Application Circuit A
Figure 18b. ADM696 Typical Application Circuit B
T
R1
R2
. The threshold should be set at a higher voltage than the
7805
R3
R4
BATTERY
+5V
BATTERY
R3
R4
NC
3V
RESET
+
R1
R2
0.1µF
PFI
LL
V
BATT
GND
LOW LINE WDO
V
OSC IN
OSC SEL
SYSTEM STATUS
PFI
LL
IN
V
BATT
ADM696
CC
INDICATORS
IN
GND
ADM696
V
BATT
CC
ON
RESET
V
PFO
WDI
OUT
RESET
V
PFO
WDI
OUT
CMOS
0.1µF
RAM
CMOS RAM
POWER
µP RESET
µP NMI
I/O LINE
µP SYSTEM
V
CC
µP POWER
I/O LINE
NMI
A0–A15
RESET
REV. 0
POWER
µP
µP