AD768 Analog Devices, AD768 Datasheet - Page 5

• Manufacturer Part Number: AD768
• Description: 16-Bit, 30 MSPS D/A Converter
• Manufacturer: Analog Devices

Specifications of AD768

• Resolution (bits): 16bit
• Dac Update Rate: 30MSPS
• Dac Settling Time: 25ns
• Max Pos Supply (v): +5.25V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

REV. B
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the ac-
tual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s. The ideal
output current span is 4 the current applied to the IREFIN pin.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
FUNCTIONAL DESCRIPTION
The AD768 is a current-output DAC with a nominal full-scale
current of 20 mA and a 1 k output impedance. Differential
outputs are provided to support single-ended or differential
applications. The DAC architecture combines segmented cur-
rent sources for the top four bits (MSBs) and a 1 k R-2R lad-
der for the lower 12 bits (LSBs). The DAC current sources are
implemented with laser-trimmable thin film resistors for excel-
lent dc linearity. A proprietary switching technique is utilized to
reduce glitch energy and maximize dynamic accuracy.
CLOCK
+5V
–5V
1µF
1µF
C
1µF
NR
16
25
26
15
5
2
V
REFCOM
V
NR
CLOCK
DCOM
DD
Figure 1. Functional Block Diagram and Basic Hookup
EE
NC
+2.5V REF
24
MSB DECODE
4
& LATCHES
23
REFOUT
C
REFCOMP
22
1µF
AD768
21
3
20
6
R
500
REFIN
19
REF
–5–
18
LATCHES – LOWER 12 BITS
The digital interface offers CMOS compatible edge-triggered
input latches that interface readily to CMOS logic and supports
clock rates up to 40 MSPS. A temperature compensated 2.5 V
bandgap reference is integrated on-chip to drive the AD768 ref-
erence input current with the use of a single external resistor.
The functional block diagram in Figure 1 is a simple representa-
tion of the internal circuitry to aid the understanding of the
AD768’s operation. The DAC transfer function is described,
and followed by a detailed description of each key portion of the
circuit. Typical circuit configurations are shown in the section
APPLYING THE AD768.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25 C) value to the value at either T
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is ex-
pressed as a percentage or in decibels (dB).
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients which are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
17
SEGMENTED
CURRENT
SOURCES
14
5mA
13
12
11
CURRENT SOURCES
AND R-2R LADDER
R
1k
10
LAD
9
R
1k
LADCOM
8
LAD
IOUTA
IOUTB
7
28
27
1
50
R
50
LOAD
IOUTA
IOUTB
MIN
AD768
or T
MAX
. For