AD7805 Analog Devices, AD7805 Datasheet
AD7805
Specifications of AD7805
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AD7805 Summary of contents
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... Automatic Calibration GENERAL DESCRIPTION The AD7804/AD7808 are quad/octal 10-bit digital-to-analog converters, with serial load capabilities, while the AD7805/AD7809 are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3 10%) power supply and incorporates an on-chip reference. ...
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... AD7804/AD7805/AD7808/AD7809 AD7804/AD7805–SPECIFICATIONS Reference = Internal Reference 100 pF Parameter B Grade STATIC PERFORMANCE MAIN DAC Resolution 10 Relative Accuracy Gain Error 2 Bias Offset Error –80/+40 3 –V Zero-Scale Error Monotonicity 9 Minimum Load Resistance 2 SUB DAC Resolution 8 Differential Nonlinearity OUTPUT CHARACTERISTICS 3 Output Voltage Range V V Voltage Output Settling Time to 10 Bits ...
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... Temperature range is – + Can be minimized using the Sub DAC the center of the output voltage swing and can be V BIAS Specifications subject to change without notice. REV. A AD7804/AD7805/AD7808/AD7809 (AV and GND. Sub DAC at Midscale. All specifications ...
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... AD7804/AD7805/AD7808/AD7809 AD7804/AD7808 TIMING CHARACTERISTICS Internal Reference. All specifications T MIN Limit at T Parameter All Versions t 100 100 9 NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with and ...
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... CS WR DATA 1 LDAC 2 LDAC CLR 1 TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2 TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE. Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write REV. A AD7804/AD7805/AD7808/AD7809 3 unless otherwise noted.) MIN MAX , T MIN ...
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... OUT Input Current to Any Pin Except Supplies Operating Temperature Range AD7804/AD7805 Commercial Plastic (B, C Versions – +85 C AD7808/AD7809 Commercial Plastic (B, C Versions – +85 C Storage Temperature Range . . . . . . . . . . . . – +150 C Junction Temperature ...
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... OUT OUT COMP 13 REFIN 12 CLR 11 CLKIN –7– AD7804/AD7805/AD7808/AD7809 /16 volts. All Sub DACs are also cleared and thus the BIAS /2 divider and is DD AD7808 PIN CONFIGURATION AGND OUT OUT ...
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... DB2 13 16 DGND 14 15 AD7805/AD7809 PIN FUNCTION DESCRIPTIONS Description No Connect. These pins should be left open circuit. Ground reference point for analog circuitry. A Analog output voltages from the DACs. Reference Output. This is a bandgap reference and is typically 1.23 V. Data Inputs. DB9 to DB2 are the 8 MSBs of the data word. ...
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... MSB first. Figure 4 shows the loading sequence for the AD7804/AD7808 system control register, Figure 5 shows the REV. A AD7804/AD7805/AD7808/AD7809 Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC ...
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... AD7804/AD7805/AD7808/AD7809 MSB X MD0 = 0 MD1 = Don’t Care Figure 4. AD7804/AD7808 System Control Register Loading Sequence DB15 (MSB) X MD0 = 1 MD1 = 0 A2 Don’t Care *Applicable to the AD7808 Only, and Are Don’t Care Conditions when Operating the AD7804 . Figure 5. AD7804/AD7808 Channel Control Register Loading Sequence ...
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... DAC G Selected DAC H Selected REV. A AD7804/AD7805/AD7808/AD7809 /2 Standby (STBY) DD This bit allows the selected DAC in the package to be put into low power mode. Writing a zero to the STBY bit in the channel /2 reference control register puts the selected DAC into standby mode. On ...
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... Figure 10. Flowchart for Controlling the DAC Following Power-Up AD7805/AD7809 INTERFACE SECTION The AD7805 and AD7809 are parallel data input devices and contain both control registers and data registers. The system control register has global control over all DACs in the package while the channel control register allows control over individual DACs in the package ...
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... DB0 registers. Table IVa shows how these DAC registers can be X MD0 = 0 addressed on the AD7805. Table IVb shows how these registers are addressed on the AD7809. Refer to Figures for infor- mation on the registers. Table IVa. AD7805 DAC Data/Control Register Selection Table ...
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... AD7805/AD7809 SYSTEM OR CHANNEL CONTROL REGISTER SELECTION MD0 0 This enables writing to the system control register. The contents of this are shown in Figure 12. Mode must be low to access this control register. 1 This enables writing to the channel control register. The contents of this are shown in Figure 13. Mode must also be low to access this control register ...
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... The flowchart in Figure 19 shows the steps necessary to control the AD7805/AD7809 following power-on. This flowchart de- tails the necessary steps when using the AD7805/AD7809 in its 10-bit parallel mode. The first step is to write to the system control register to clear the SSTBY bit and to configure the part for 10-bit parallel mode and select the required coding scheme ...
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... The LDAC input condition is sampled on the sixteenth falling edge on the AD7804/AD7808 and is sampled on the rising edge of write on the AD7805/AD7809. If LDAC is low on the sixteenth falling clock edge or on the rising edge of WR, an automatic or synchronous update will take place. ...
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... DAC. REV. A AD7804/AD7805/AD7808/AD7809 Configuring the AD7805/AD7809 for Twos Complement Coding Figure 24 shows a typical configuration for the AD7805/AD7809. The circuit can be used for either 3 operation and uses the internal V lel interfacing is used. The following are the steps required to operate the Main DACs in this part. ...
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... AD7804/AD7805/AD7808/AD7809 Table VI and Figure 22 show the analog outputs available for the above configuration. The following is the procedure re- quired if the complete transfer function needs to be offset around the V point. Table VII and Figure 23 show the ana- BIAS log output variations available from the Sub DAC. ...
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... The MX1 and MX0 bits in the system control register have to be set to enable selection of the AD589 as the reference. The following are the steps required to operate the DACs in this part. Figures show the contents of the registers on the AD7804/AD7808. REV. A AD7804/AD7805/AD7808/AD7809 127/256 0.01 F 126/256 1/256 0.01 F ...
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... On the AD7805 the REFOUT pin of the device is located next to the DB9 of the data bus, to reduce the risk of digital feed- through and noise being coupled from the digital section onto ...
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... Typical Performance Characteristics–AD7804/AD7805/AD7808/AD7809 0.150000 MAIN DAC = ZERO SCALE SUB DAC = MID SCALE 0.125000 BIAS + 0.100000 V = 5.5V DD 0.075000 0.050000 DD 0.025000 SOURCE CURRENT SINK CURRENT 0.000000 –0.5 –0.4 –0.3 –0.2 –0.1 0.0 CURRENT – mA Figure 29. Sink and Source Current with Zero Scale Loaded to DAC ...
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... AD7804/AD7805/AD7808/AD7809 MICROPROCESSOR INTERFACING AD7804/AD7808–ADSP-2101/ADSP-2103 Interface Figure 35 shows a serial interface between the AD7804/AD7808 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP- 2103 should be set up to operate in the SPORT Transmit Alter- nate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-bit Word Length ...
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... CONTAINED ON THE AD7809 ONLY Figure 39. AD7805/AD7809–TMS32020 Interface REV. A AD7804/AD7805/AD7808/AD7809 Again fast interface timing allows the AD7805/AD7809 inter- face directly to the processor. Data is loaded to the AD7805/ AD7809 input latch using the following instruction: OUT DAC, D. DAC = Decoded DAC Address Data Memory Address. ...
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... AD7805 As a Digitally Programmable Window Detector V B OUT A digitally programmable upper/lower limit detector using two DACs in the AD7805 is shown in Figure 43. The upper and V C OUT lower limits for the test are loaded to DACs A and B that in turn set the limits on the CMP04 signal at the V ...
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... The AD7805 in the circuit is used to control the attenuation of the VCA, this application circuit only gives attenuation. The voltage output from the AD7805 provides a low impedance drive to the SSM2164 so attenuation can be controlled accurately ...
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... Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 21 Microprocessor Interfacing ADSP-2101/ADSP-2103 . . . . . . . . . . . . . . . . . . . . . . . . . 22 68HC11/68L11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 80C51/80L51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications Opto-Isolated Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Decoding Multiple ICs . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 28 PAGE INDEX (AD7805/AD7809 PARALLEL INTERFACE PART) Page No. Topic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Timing Information Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Function Description ...
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... AD7804/AD7805/AD7808/AD7809 Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93 0.280 (7.11) 0.240 (6.10 0.060 (1.52) PIN 1 0.015 (0.38) MAX 0.130 (3.30) MIN 0.100 0.070 (1.77) SEATING 0.022 (0.558) PLANE (2 ...
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... AD7804/AD7805/AD7808/AD7809 Plastic DIP (N-24 PIN 1.275 (32.30) 1.125 (28.60) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.100 (2.54) 0.070 (1.77) 0.014 (0.356) BSC 0.045 (1.15) SOIC (R-24) 0.614 (15.6) 0.598 (15. 0.299 (7.6) 0.291 (7. PIN 1 0.104 (2.65) 0.093 (2.35) 0.012 (0.3) 0.0500 (1.27) 0.019 (0.49) SEATING 0.013 (0.32) BSC PLANE 0.004 (0.1) 0.014 (0.35) 0.009 (0.25) OUTLINE DIMENSIONS Dimensions shown in inches and (mm) ...