AD5313 Analog Devices, AD5313 Datasheet - Page 23

• Manufacturer Part Number: AD5313
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5313

• Resolution (bits): 10bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

COARSE AND FINE ADJUSTMENT USING THE
AD5303/AD5313/AD5323
The DACs in the AD5303/AD5313/AD5323 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 45. DAC A provides the coarse adjustment
while DAC B provides the fine adjustment. Varying the ratio
of R1 and R2 changes the relative effect of the coarse and fine
adjustments. With the resistor values and external reference
shown, the output amplifier has unity gain for the DAC A
output, so the output range is 0 V to 2.5 V − 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 10
a range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference
voltages up to V
a rail-to-rail output swing.
AD780/REF192
WITH V
DAISY-CHAIN MODE
This mode is used for updating serially connected or standalone
devices on the rising edge of SYNC . For systems that contain
several DACs, or where the user wishes to read back the DAC
contents for diagnostic purposes, the SDO pin may be used to
daisy-chain several devices together and provide serial readback.
By connecting the daisy-chain enable (DCEN) pin high, the
daisy-chain mode is enabled. It is tied low in standalone mode.
In daisy-chain mode, the internal gating on SCLK is disabled.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 16 clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out after the falling edge of SCLK and
is valid on the subsequent rising and falling edges. By connect-
ing this line to the DIN input on the next DAC in the chain, a
multiDAC interface is constructed. Sixteen clock pulses are
required for each DAC in the system. Therefore, the total
number of clock cycles must equal 16N, where N is the total
number of devices in the chain. When the serial transfer to all
devices is complete, SYNC should be taken high. This prevents
any further data from being clocked into the input shift register.
EXT 2.5V
REF
GND
V
IN
DD
V
OUT
= 5V
0.1µF
1µF
Figure 45. Coarse and Fine Adjustment
DD
may be used. The op amps indicated allow
V
AD5303/AD5313/
10µF
V
REF
REF
A
B
AD5323
V
DD
GND
V
DD
= 5V
V
V
OUT
OUT
51.2kΩ
B
A
R3
51.2kΩ
390Ω
R1
R2
–3
, giving DAC B
900Ω
+5V
R4
AD820/
OP295
V
Rev. B | Page 23 of 28
OUT
A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of
clock cycles may be used and SYNC may be taken high some
time later.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.
68HC11
MISO
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Daisy-Chain Mode
MOSI
1
SCK
PC7
PC6
AD5303/AD5313/AD5323
DIN
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
AD5323
AD5323
AD5323
AD5303/
AD5313/
AD5303/
AD5313/
AD5303/
AD5313/
SDO
SDO
SDO
DIN
DIN
(DAC N)
(DAC 1)
(DAC 2)
1
1
1