AD5313 Analog Devices, AD5313 Datasheet - Page 20

• Manufacturer Part Number: AD5313
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5313

• Resolution (bits): 10bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5303/AD5313/AD5323
MICROPROCESSER INTERFACING
AD5303/AD5313/AD5323 TO ADSP-2101
INTERFACE
Figure 35 shows a serial interface between the AD5303/AD5313/
AD5323 and the ADSP-2101. The ADSP-2101 should be set up
to operate in the SPORT transmit alternate framing mode. The
ADSP-2101 sport is programmed through the SPORT control
register and should be configured as follows: internal clock
operation, active-low framing, 16-bit word length. Transmission
is initiated by writing a word to the Tx register after the SPORT
has been enabled.
AD5303/AD5313/AD5323 TO 68HC11/68L11
INTERFACE
Figure 36 shows a serial interface between the AD5303/
AD5313/AD5323 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5303/
AD5313/AD5323, while the MOSI output drives the serial data
line (DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 should be con-
figured so that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is being transmitted to the DAC, the SYNC line
is taken low (PC7). When the 68HC11/68L11 is configured
as previously mentioned, data appearing on the MOSI output
is valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5303/AD5313/ AD5323, PC7 is left
low after the first eight bits are transferred and a second serial
write operation is performed to the DAC; PC7 is taken high at
the end of this procedure.
Figure 36. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface
Figure 35. AD5303/AD5313/AD5323 to ADSP-2101 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
68HC11/68L11*
ADSP-2101
SCLK
MOSI
SCK
PC7
TFS
DT
SYNC
DIN
SCLK
SYNC
SCLK
DIN
AD5323*
AD5303/
AD5313/
AD5303/
AD5313/
AD5323*
Rev. B | Page 20 of 28
AD5303/AD5313/AD5323 TO 80C51/80L51
INTERFACE
Figure 37 shows a serial interface between the AD5303/
AD5313/AD5323 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TXD of the 80C51/80L51
drives SCLK of the AD5303/AD5313/AD5323, while RXD
drives the serial data line of the part. The SYNC signal is again
derived from a bit programmable pin on the port. In this case,
port line P3.3 is used. When data is to be transmitted to the
AD5303/AD5313/AD5323, P3.3 is taken low. The 80C51/80L51
transmits data only in 8-bit bytes; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 output the serial data in a format that has the LSB first.
The AD5303/AD5313/AD5323 require data with MSB as the
first bit received. The 80C51/80L51 transmit routine should
take this into account.
AD5303/AD5313/AD5323 TO MICROWIRE
INTERFACE
Figure 38 shows an interface between the AD5303/AD5313/
AD5323 and any MICROWIRE-compatible device. Serial
data is shifted out on the falling edge of the serial clock and
is clocked into the AD5303/AD5313/AD5323 on the rising
edge of the SK.
Figure 37. AD5303/AD5313/AD5323 to 80C51/80L51 Interface
Figure 38. AD5303/AD5313/AD5323 to MICROWIRE Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
MICROWIRE*
P3.3
RXD
TXD
CS
SK
SO
SYNC
SCLK
DIN
SYNC
SCLK
DIN
AD5323*
AD5323*
AD5303/
AD5313/
AD5303/
AD5313/