AD9709 Analog Devices, AD9709 Datasheet - Page 15

• Manufacturer Part Number: AD9709
• Description: 8-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9709

• Resolution (bits): 8bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

DIGITAL INPUTS
The digital inputs of the AD9709 consist of two independent
channels. For the dual port mode, each DAC has its own
dedicated 8-bit data port: WRT line and CLK line. In the
interleaved timing mode, the function of the digital control pins
changes as described in the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7P1 and DB7P2 are the most significant bits (MSBs)
and DB0P1 and DB0P2 are the least significant bits (LSBs).
I
at Logic 1. I
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
The AD9709 can operate in two timing modes, dual and
interleaved, which are described in the following sections. The
block diagram in Figure 25 represents the latch architecture in
the interleaved timing mode.
Dual Port Mode Timing
When the MODE pin is at Logic 1, the AD9709 operates in dual
port mode (refer to Figure 21). The AD9709 functions as two
distinct DACs. Each DAC has its own completely independent
digital input and control lines.
The AD9709 features a double-buffered data path. Data enters the
device through the channel input latches. This data is then trans-
ferred to the DAC latch in each signal path. After the data is loaded
into the DAC latch, the analog output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
IQWRT
IQSEL
OUTA
DATA IN, PORT 1
INTERLEAVED
produces a full-scale output current when all data bits are
IQRESET
IQCLK
OUTB
Figure 25. Latch Structure in Interleaved Mode
produces a complementary output with the
PORT 2
PORT 1
LATCH
LATCH
INPUT
INPUT
÷2
DAC1
LATCH
DAC2
LATCH
DAC1
DAC2
DEINTERLEAVED
DATA OUT
Rev. B | Page 15 of 32
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns should
be maintained from rising edge of WRT to rising edge of CLK.
Timing specifications for dual port mode are given in Figure 26
and Figure 27.
Interleaved Mode Timing
When the MODE pin is at Logic 0, the AD9709 operates in
interleaved mode (refer to Figure 25). In addition, WRT1
functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The
logic level of IQSEL steers the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
Similar to the order of CLK and WRT in dual port mode,
IQCLK should occur before or simultaneously with IQWRT.
WRT1/WRT2
CLK1/CLK2
WRT1/WRT2
CLK1/CLK2
DATA IN
DATA IN
I
I
OUTA
OUTB
I
I
OR
OUTA
OUTB
OR
D1
Figure 26. Dual Port Mode Timing
Figure 27. Dual Mode Timing
XX
D2
t
S
D1
D3
t
PD
D2
D4
t
H
t
t
LPW
CPW
D3
D5
AD9709
D4