AD9709 Analog Devices, AD9709 Datasheet - Page 12

• Manufacturer Part Number: AD9709
• Description: 8-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9709

• Resolution (bits): 8bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9709
THEORY OF OPERATION
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9709. The
AD9709 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (I
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources instead of an R-2R
ladder enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
I
Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
REF
R
SET
DCOM1/DCOM2
2kΩ
DVDD1/DVDD2
1
I
REF
1
2
R
2kΩ
SET
0.1µF
R
RETIMED CLOCK OUTPUT*
SET
R
2kΩ
0.1µF
1
2kΩ
SET
2
2
LECROY 9210
GENERATOR
FSADJ1
REFIO
FSADJ2
PULSE
FSADJ1
REFIO
FSADJ2
GAINCTRL
GAINCTRL
1.2V REF
1.2V REF
OUTFS
50Ω
AD9709
IQWRT
WRT1/
IQWRT
WRT1/
CURRENT
CURRENT
).
CURRENT
CURRENT
SOURCE
SOURCE
SOURCE
SOURCE
ARRAY
ARRAY
ARRAY
ARRAY
PMOS
PMOS
AVDD
PMOS
PMOS
AVDD
5V
5V
CHANNEL 1 LATCH
CHANNEL 1 LATCH
WITH OPTION 4
TEKTRONIX
AWG2021
PORT 1
DIGITAL
PORT 1
DATA
DIGITAL DATA INPUTS
MULTIPLEXING LOGIC
DIVIDER
MULTIPLEXING LOGIC
DIVIDER
Figure 22. Simplified Block Diagram
th
CLK
CLK
of an
LATCH
LATCH
DAC1
DAC1
Rev. B | Page 12 of 32
CLK1/IQCLK
CLK1/IQCLK CLK2/IQRESET
LATCH
LATCH
DAC2
DAC2
CHANNEL 2 LATCH
CHANNEL 2 LATCH
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
PORT 2
PORT 2
SWITCHES FOR
SWITCHES FOR
SWITCHES FOR
SWITCHES FOR
SEGMENTED
SEGMENTED
SEGMENTED
SEGMENTED
CLK2/IQRESET
All of these current sources are switched to one of the two
output nodes (that is, I
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9709 have separate
power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
DAC1
DAC2
DAC1
DAC2
WRT2/
IQSEL
WRT2/
IQSEL
AD9709
DCOM1/
DCOM2
SWITCH
SWITCH
SWITCH
SWITCH
LSB
LSB
LSB
LSB
SLEEP
SLEEP
MODE
DCOM1/
DVDD1/
DCOM2
DVDD1/
DVDD2
DVDD2
ACOM
ACOM
I
I
I
I
I
I
I
I
MODE
OUTA1
OUTB1
OUTA2
OUTB2
OUTA1
OUTB1
OUTA2
OUTB2
OUTA
or I
5V
V
OUT
5V
50Ω
50Ω
OUTB
V
2B
R
50Ω
DIFF
L
Mini-Circuits
2B
) via the PMOS differential
V
= V
T1-1T
OUT
OUT
R
50Ω
2A
L
A – V
2A
V
OUT
OUT
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
R
50Ω
1B
L
B
1B
V
OUT
R
50Ω
1A
L
1A