AD9755 Analog Devices, AD9755 Datasheet - Page 18

• Manufacturer Part Number: AD9755
• Manufacturer: Analog Devices

Specifications of AD9755

• Resolution (bits): 14bit
• Dac Update Rate: 300MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9755
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 34 to 41 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9755 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
common in applications where the power distribution is generated
by a switching power supply. Typically, switching power supply
noise occurs over the spectrum from tens of kHz to several MHz.
The PSRR versus frequency of the AD9755 AVDD su
this frequency range is shown in Figure 25.
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output current.
The voltage noise on AVDD thus is added in a nonlinear manner
to the desired I
switches, PSRR is very code-dependent. This can produce a
85
80
75
70
65
60
55
50
45
40
Figure 25. Power Supply Rejection Ratio
0
OUT
2
. Due to the relative different size of these
4
FREQUENCY (MHz)
OUTFS
. AC noise on the dc supplies is
6
8
10
pply over
12
–18–
mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occurs when the full-scale current is
directed toward that output. As a result, the PSRR measurement
in Figure 25 represents a worst-case condition in which the
digital inputs remain static and the full-scale output current of
20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, I
using Figure 25 at 250 kHz. To calculate the PSRR for a given
R
V/V, adjust the curve in Figure 25 by the scaling factor 20 × Log
(R
34 dB, i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 25, becomes 51 dB V
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9755 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a system.
In general, AVDD, the analog supply, should be decoupled to
ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be decoupled
to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply and
return lines. Lower noise can be attained by using low ESR type
electrolytic and tantalum capacitors.
Figure 26. Differential LC Filter for a Single 3.3 V Application
LOAD
LOAD
TTL/CMOS
CIRCUITS
POWER SUPPLY
LOGIC
, such that the units of PSRR are converted from A/V to
). For instance, if R
3.3V
OUTFS
FERRITE
BEADS
, one must determine the PSRR in dB
LOAD
ELECT.
100 F
OUT
is 50 Ω, the PSRR is reduced by
/V
IN
10 F-22 F
.
TANT.
0.1 F
CER.
REV. B
AVDD
ACOM