AD9755 Analog Devices, AD9755 Datasheet
AD9755
Specifications of AD9755
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AD9755 Summary of contents
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... CMOS process. It operates from a single supply of 3 3.6 V and consumes 155 mW of power. PRODUCT HIGHLIGHTS 1. The AD9755 is a member of a pin compatible family of high speed TxDAC+s providing 10-, 12-, and 14-bit resolution. 2. Ultrahigh Speed 300 MSPS Conversion Rate. 3. Dual 14-Bit Latched, Multiplexed Input Ports. The AD9755 features a flexible digital interface allowing high speed data conversion through either a single or dual port input ...
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... AD9755 ( MIN DC SPECIFICATIONS otherwise noted.) Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance ...
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... Specifications subject to change without notice. REV AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3 MIN MAX Differential Transformer-Coupled Output, 50 Min ) 300 83.5 –3– AD9755 = 20 mA, OUTFS Doubly Terminated, unless otherwise noted.) Typ Max Unit MSPS pV-s 2 pA/√Hz 30 pA/√ ...
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... AD9755 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Logic 0 Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time ( 25° Input Hold Time ( 25° Latch Pulsewidth ( 25°C LPW A Input Setup Time (t PLLVDD = 0 V Input Hold Time (t PLLVDD = 0 V), T ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9755 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... PLLVDD 48 CLKVDD PIN CONFIGURATION RESET 1 PIN 1 CLK+ 2 IDENTIFIER CLK– 3 DCOM 4 DVDD 5 AD9755 PLLLOCK 6 TOP VIEW 7 (Not to Scale) P1B12 8 P1B11 9 P1B10 10 P1B9 11 P1B8 PIN FUNCTION DESCRIPTIONS Description Internal Clock Divider Reset ...
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... CLK– DIGITAL DATA INPUTS MINI TEKTRONIX DG2020 CIRCUITS OR T1-1T AWG2021 w/OPTION 4 PLL ENABLED LECROY 9210 PULSE GENERATOR PLL DISABLED (FOR DATA RETIMING) Figure 2. Basic AC Characterization Test Setup –7– AD9755 MINI TO ROHDE & CIRCUITS SCHWARZ I T1-1T OUTA FSEA30 SPECTRUM I OUTB 50 ANALYZER PLLVDD ...
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... AD9755–Typical Performance Characteristics 90 0dBmFS 80 –6dBmFS 70 –12dBmFS (MHz) OUT TPC 1. Single-Tone SFDR vs OUT MSPS; Single Port Mode DAC 90 65MSPS 80 200MSPS 70 60 300MSPS 100 120 140 f (MHz) OUT TPC 4. SFDR vs dBFS ...
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... OUTFS DAC 300 MSPS @ 0 dBFS –1 0 2048 6144 10240 14336 4096 8192 12288 16383 CODE TPC 17. Typical DNL –9– AD9755 90 26MHz/27MHz 80 @ 130MSPS 70 60 40MHz/41MHz @ 200MSPS 50 60MHz/61MHz @ 300MSPS 40 –20 –18 –16 –14 –12 –10 –8 –6 –4 – (dBm) OUT TPC 12 ...
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... AD9755 FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9755. The AD9755 consists of a PMOS current source array capable of providing full-scale current, I divided into 31 equal sources that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... CLKCOM disabling the PLL clock multiplier to achieve the best SNR performance from the AD9755. Note that the SFDR performance of the AD9755 remains unaffected with or without the PLL clock multiplier enabled. –11– t ...
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... The speed and timing of the data present at input Ports 1 and 2 are now dependent on whether or not the AD9755 is interleaving the digital input data, or only responding to data on a single port. Figure functional block diagram of the AD9755 clock control circuitry with the PLL disabled. ...
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... PLLLOCK. REV. B NONINTERLEAVED MODE WITH PLL DISABLED If the data at only one port is required, the AD9755 interface can operate as a simple double buffered latch with no interleaving. On the rising edge of the 1× clock, input latch updated with the present input data (depending on the state of DIV0/ DIV1) ...
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... OUTB shown in Figures 7 and 11. The AD9755 is designed to support an input data rate as high as 150 MSPS, giving a DAC output update rate of 300 MSPS. The setup-and-hold times can also be varied within the clock cycle as long as the specified minimum times are met ...
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... Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. Inserting a low value resistor network (i.e., 20 Ω to 100 Ω) between the AD9755 digi- tal inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough ...
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... APPLYING THE AD9755 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9755. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration ...
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... In this case, AVDD, which is the positive analog supply for both the AD9755 and the op amp, is also used to level-shift the differ- ential output of the AD9755 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... Figure 25, becomes Proper grounding and decoupling should be a primary objective pply over in any high speed, high resolution system. The AD9755 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible ...
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... In Figure 28, the adjacent channel power ratio (ACPR) at the output of the AD9755 is measured dB. The limitation on making a measurement of this type is often not the DAC but the noise inherent in creating the digital data record using computer tools ...
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... QAM with the BER of 1e-6, using the E/N ratio is much greater than the worst-case SFDR, the noise will dominate the BER calculation. The AD9755 has a worst-case in-band SFDR the upper end of its frequency spectrum (see TPCs 2, 3). When CU1 ...
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... A clock can also be applied via the ribbon cable on Port 1 (P1), Pin 33. By inserting the EDGE jumper (JP1), this clock will be applied to the CLK+ input of the AD9755. JP3 should be set in its SE position in this application to bias CLK– to half the supply voltage. ...
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... P1B07 1B05 13 P1B06 3 14 1B04 P1B05 4 15 1B03 P1B04 16 5 P1B03 1B02 17 P1B02 6 18 1B01 P1B01 19 AD9751/AD9753/AD9755 7 P1B00 LSB 1B00 DVDD PLANE 1O16 9 22 JP10 23 MSB 10 P2B13 24 1O17 P2B12 P2B11 RN9 P2B10 VALUE P2B09 ...
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... AVDD PLANE TP16 BLK TP17 RED CLKVDD JP7 TP11 PLLVDD PLANE B BLK 3 Figure 35. Evaluation Board Clock Circuitry Figure 36. Evaluation Board, Assembly—Top –23– AD9755 CLK JP4 PGND BYPASS CAPS PINS 5, 6 PINS 21 ...
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... AD9755 Figure 37. Evaluation Board, Assembly—Bottom Figure 38. Evaluation Board—Top Layer –24– REV. B ...
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... Figure 39. Evaluation Board, Layer 2, Ground Plane Figure 40. Evaluation Board, Layer 3, Power Plane REV. B –25– AD9755 ...
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... AD9755 Figure 41. Evaluation Board, Bottom Layer –26– REV. B ...
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... REV. B OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 1 SEATING 10 PLANE 6 0.20 2 0.09 VIEW 0.08 MAX 0.50 COPLANARITY BSC VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC –27– AD9755 9.00 BSC PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN 0.27 0.22 0.17 ...
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... AD9755 Revision History Location 6/03—Data Sheet changed from REV REV. B. Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure Changes to FUNCTIONAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure Changes to Figure Changes to Figure Changes to DIGITAL INPUTS section ...