AD9773 Analog Devices, AD9773 Datasheet - Page 28

• Manufacturer Part Number: AD9773
• Manufacturer: Analog Devices

Specifications of AD9773

• Resolution (bits): 12bit
• Dac Update Rate: 400MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9773
LATCHES
INTERPOLATION
LATCHES
INTERPOLATION
In addition, if the zero stuffing option is enabled, the VCO
doubles its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 47 illustrates typical phase noise
performance of the AD9773 with 2× interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of f
repetitive nature of this signal eliminates quantization noise and
distortion spurs as a factor in the measurement. Although the
curves blend together in Figure 47, the different conditions are
given for clarity in Table 17. Table 16 details PLL divider
settings vs. interpolation rate and maximum and minimum
f
due to the maximum input data rate of the AD9773.
DATA
CONTROL
INPUT
INPUT
CONTROL
DATA
DATA
RATE
RATE
rates. Note that the maximum f
1
1
Figure 46. PLL and Clock Circuitry with PLL Disabled
Figure 45. PLL and Clock Circuitry with PLL Enabled
2
2
0 = NO LOCK
0 = NO LOCK
PLL_LOCK
PLL_LOCK
DISTRIBUTION
DISTRIBUTION
INTERPOLATION
INTERPOLATION
1 = LOCK
MODULATORS,
INTERNAL SPI
1 = LOCK
MODULATORS,
INTERNAL SPI
CIRCUITRY
CIRCUITRY
SPI PORT
REGISTERS
REGISTERS
SPI PORT
4
4
AND DACS
CONTROL
CONTROL
CLOCK
AND DACS
CLOCK
FILTERS,
FILTERS,
8
8
CLK+
CLK+
MODULATION
MODULATION
CONTROL
CONTROL
RATE
RATE
CLK–
CLK–
PRESCALER
DETECTOR
PRESCALER
DETECTOR
PHASE
PHASE
DATA
AD9773
rates of 160 MSPS are
CONTROL
CONTROL
(PLL ON)
(PLL ON)
(PRESCALER)
(PRESCALER)
AD9773
PLL DIVIDER
PLL DIVIDER
PLL
PLL
CONTROL
CONTROL
CHARGE
CHARGE
PUMP
PUMP
VCO
VCO
PLLVDD
DATA
/4. The
LPF
Rev. D | Page 28 of 60
However, maximum rates of less than 160 MSPS and all
minimum f
speeds of the internal PLL VCO. Figure 48 shows typical
performance of the PLL lock signal (Pin 8 or Pin 53) when the
PLL is in the process of locking.
Table 16. PLL Optimization
Interpolation
Rate
1
1
1
1
2
2
2
2
4
4
4
4
8
8
8
8
Table 17. Required PLL Prescaler Ratio vs. f
f
125 MSPS
125 MSPS
100 MSPS
75 MSPS
50 MSPS
DATA
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
DATA
rates are due to the maximum and minimum
1
Figure 47. Phase Noise Performance
Divider
Setting
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
PLL
Disabled
Enabled
Enabled
Enabled
Enabled
FREQUENCY OFFSET (MHz)
2
Minimum
f
32
16
8
4
24
12
6
3
24
12
6
3
24
12
6
3
DATA
3
Prescaler Ratio
Div 1
Div 2
Div 2
Div 4
4
DATA
Maximum
f
160
160
112
56
160
112
56
28
100
56
28
14
50
28
14
7
DATA
5