AD9773 Analog Devices, AD9773 Datasheet
AD9773
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AD9773 Summary of contents
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Dual TxDAC D/A Converter IDAC COS GAIN DAC SIN IMAGE REJECTION/ I/Q DAC DUAL DAC GAIN/OFFSET MODE REGISTERS BYPASS MUX SIN COS IDAC ) DIFFERENTIAL CLK ©2007 Analog Devices, Inc. All rights reserved. AD9773 OFFSET DAC I OUT www.analog.com ...
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... Image Rejection and Sideband Suppression of Modulated Carriers ........................................................................................ 41 Applying the Output Configurations........................................... 46 Unbuffered Differential Output, Equivalent Circuit ............. 46 Differential Coupling Using a Transformer............................ 46 Differential Coupling Using an Op Amp................................ 47 Interfacing the AD9773 with the AD8345 Quadrature Modulator.................................................................................... 47 Evaluation Board ............................................................................ 48 Outline Dimensions ....................................................................... 58 Ordering Guide .......................................................................... 58 Changes to Figure 108 .................................................................. 54 Updated Outline Dimensions ...
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... Edits to Figure 22 .......................................................................... 25 Edits to Figure 23 .......................................................................... 26 Edits to Figure 26a ........................................................................ 27 Edits to Complex Modulation and Image Rejection of Baseband Signals Section ............................................................. 31 Changes to Figures 53 and 54...................................................... 38 Edits to Evaluation Board Section .............................................. 39 Changes to Figures 56 through 59 .............................................. 40 Replaced Figures 60 through 69.................................................. 42 Updated Outline Dimensions...................................................... 49 Rev Page AD9773 ...
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... The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems. PRODUCT HIGHLIGHTS 1. The AD9773 is the 12-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. 2. Direct IF transmission is possible for 70 MHz + IFs ...
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... Rev Page AD9773 Unit Bits LSB LSB % of FSR % of FSR % of FSR mA V kΩ kΩ MHz ppm of FSR/°C ppm of FSR/°C ppm/° FSR/V °C ...
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... AD9773 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = MIN MAX transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (f Output Settling Time (t ) (to 0.025 Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) ...
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... Rev Page mA, unless otherwise noted. OUTFS Min Typ Max 2 0.9 −10 +10 −10 + 0.75 1.5 2.25 0.5 1 1.5 2 0.9 −10 +10 −10 +10 5 DRVDD − 0.6 0 AD9773 Unit V V μA μ MHz μA μ ...
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... AD9773 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient − −134 244 10 11, 33 −414 12 13, 31 673 14 15, 29 −1079 16 17, 27 1772 18 19, 25 −3280 20, 24 ...
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... DGND −0.3 CLKGND −0.3 CLKGND −0.3 DGND −0.3 −65 THERMAL CHARACTERISTICS Thermal Resistance 80-lead thin quad flat package, exposed pad (TQFP_EP) θ = 23.5°C/W (with thermal pad soldered to PCB) JA ESD CAUTION Rev Page AD9773 Max Unit +4.0 V +4.0 V +0.3 V AVDD + 0.3 V AVDD + 0.3 V DVDD + 0.3 V DVDD + 0.3 V CLKVDD + 0 ...
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... P1B8 P1B7 P1B6 DGND DVDD P1B5 P1B4 CONNECT PIN AD9773 8 TxDAC+ 9 TOP VIEW (Not to Scale Figure 5 ...
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... In two-port mode, this pin becomes the Port 2 MSB. With the PLL disabled and the AD9773 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9773 to accept and demux interleaved I and Q data to the I and Q input registers. ...
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... AD9773 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Ω doubly terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ MSPS with f DATA 90 85 0dBFS 80 75 –6dBFS 70 –12dBFS ...
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... MSPS Figure 16. Third-Order IMD Products vs 160 MSPS Figure 17. Third-Order IMD Products vs. f Rev Page AD9773 –3dBFS –6dBFS 0dBFS FREQUENCY (MHz MSPS OUT DATA –6dBFS 0dBFS –3dBFS FREQUENCY (MHz) ...
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... AD9773 90 8× 85 4× 1× 70 2× FREQUENCY (MHz) Figure 18. Third-Order IMD Products vs. f OUT 1× 160 MSPS, 2× 160 MSPS, 4× f DATA DATA 8× MSPS DATA 90 4× 8× 2× 1× ...
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... Figure 28. Single-Tone Spurious Performance –20 –40 –60 –80 200 250 –100 0 Figure 29. Two-Tone IMD Performance MHz, OUT Rev Page AD9773 FREQUENCY (MHz) = 150 MSPS, Interpolation = 4× DATA 50 100 150 200 FREQUENCY (MHz MHz, ...
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... AD9773 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100 200 FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance MSPS, Interpolation = 8× DATA 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 300 Figure 31. Eight-Tone IMD Performance MHz, OUT Rev ...
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... For reference drift, the drift is reported in ppm per °C. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental expressed as a percentage or in decibels (dB). Rev Page AD9773 For offset and gain MIN MAX ...
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... AD9773 MODE CONTROL (VIA SPI PORT) 1 Table 9. Mode Control via SPI Port Address Bit 7 Bit 6 00h SDIO LSB, MSB First Bidirectional 0 = MSB 0 = Input 1 = LSB 1 = I/O 01h Filter Filter Interpolation Interpolation Rate Rate (1×, 2×, 4×, 8×) (1×, 2×, 4×, 8×) 02h 0 = Signed ...
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... Coarse Gain Adjustment QDAC QDAC QDAC Offset Offset Offset Adjustment Adjustment Adjustment Bit 7 Bit 6 Bit 5 Version Register Rev Page AD9773 Bit 2 Bit 1 Bit 0 QDAC QDAC QDAC Coarse Gain Coarse Gain Coarse Gain Adjustment Adjustment Adjustment QDAC QDAC QDAC Offset Offset ...
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... FULLSCALE2 as twos complement. Logic 1 causes data to be accepted as straight binary. Bit 6: Logic 0 (default) places the AD9773 in two-port mode. I and Q data enters the AD9773 via Port 1 and Port 2, respectively. A Logic 1 places the AD9773 in one-port mode in which interleaved I and Q data is applied to Port 1. See Table 8 for detailed information on the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes ...
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... Rev Page and function of fine gain, OUTA OUTB is created by a single FSADJ1 resistor REF ⎤ ⎞ ⎟ ⎥ ⎠ ⎦ ⎤ ⎞ − 1 ⎟ ⎟ ⎥ ⎥ 2 ⎠ ⎦ AD9773 . OUTB (1) ...
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... GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9773. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9773 coincident with the first eight SCLK rising edges. The instruction byte provides the ...
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... This functionality is controlled by the first LSB bit in Register 0. The default is MSB first. LSB When this bit is set active high, the AD9773 serial port is in LSB first format. In LSB first mode, the instruction byte and data ...
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... PWH PWL INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 35. Timing Diagram for Register Write to AD9773 t DV DATA BIT N DATA BIT N–1 Figure 36. Timing Diagram for Register Read from AD9773 Rev Page DATA TRANSFER CYCLE ...
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... NOTES ON SERIAL PORT OPERATION The AD9773 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h important to note that the config- uration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle ...
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... LO leakage resulting from modulation of dc signal components. If the AD9773 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9773 as well as the input offset on the modulator. Figure 42 shows a typical example of the effect that the offset control has on LO suppression. ...
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... Figure 44. Differential Clock Driving Clock Inputs A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is used on the AD9773 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. PECL/ECL drivers require varying termination networks, the ...
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... Note that the maximum f DATA DATA due to the maximum input data rate of the AD9773. However, maximum rates of less than 160 MSPS and all minimum f PLLVDD speeds of the internal PLL VCO. Figure 48 shows typical ...
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... Process of Locking (Typical Lock Time important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9773. This suffices unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF and CLKVDD pins. ...
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... When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9773 on the rising edge of the CLKIN. Figure 52 shows the delay, t inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2 ...
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... I and Q channels. The selection of the data for the channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9773 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel ...
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... CLKIN. Internal clock dividers in the AD9773 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9773 on the rising edge of DATACLK. DATACLK speed is defined as the ...
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... The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9773 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than out-of-band rejection ...
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... AD9773 MODULATION, NO INTERPOLATION With Control Register 01h, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9773 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9773 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4 ...
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... MODULATION, INTERPOLATION = 2× With Control Register 01h, Bit 7 and Bit 6 set to 01, the inter- polation rate of the AD9773 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9773 DAC output with 2× ...
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... AD9773 MODULATION, INTERPOLATION = 4× With Control Register 01h, Bit 7 and Bit 6 set to 10, the inter- polation rate of the AD9773 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). The Effects of the Digital Modulation on the DAC Output Spectrum Interpolation = 4× ...
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... Figure 71 to Figure 74 represent the spectral response of the AD9773 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8× ...
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... DAC This image may be the desired signal application using one of the various modulation modes in the AD9773. This roll- off of image frequencies can be seen in Figure 59 to Figure 74, where the effect of the interpolation and modulation rate is apparent as well ...
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... It is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the AD9773 input channels. In fact, image rejection still occurs with either one or both of the AD9773 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could be suppressed while passing the lower one ...
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... AD9773 REAL CHANNEL (IN IMAGINARY CHANNEL (IN REAL QUADRATURE MODULATOR IMAGINARY COMPLEX MODULATION FREQUENCY QUADRATURE MODULATION FREQUENCY Q REAL CHANNEL (OUT) A – C –B/2J f – C COMPLEX IMAGINARY CHANNEL (OUT) MODULATOR –A/2J f – C B/2 f – C A/4 + B/4J A/4 – B/ – – ...
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... Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9773 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator results in severe distortion at the DAC output ...
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... Region C remain. This image appears on the real /4 and f /8. DAC DAC and imaginary outputs of the AD9773, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents the quadrature modulator LO and the horizontal scale represents the frequency offset from this LO. Region D jω ...
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... Modulation DAC –3.0 –2.0 –1.0 0 1.0 2.0 3.0 (LO (× ) OUT DATA Figure 87. 4x Interpolation, Complex f /8 Modulation DAC –6.0 –4.0 –2.0 0 2.0 4.0 6.0 (LO (× ) OUT DATA Figure 88. 8x Interpolation, Complex f /8 Modulation DAC AD9773 8.0 ...
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... FREQUENCY (MHz) Figure 89. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4x, No Modulation in AD9773 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 750 ...
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... Figure 96. AD9773 Complex Output from Figure 95, Now Quadrature Modulated Rev Page FREQUENCY (MHz) Baseband (Positive Frequencies Only), Interpolation = 8x, Complex Modulation in AD9773 = +f DAC 720 740 760 780 ...
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... In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 97 illustrates the output of the AD9773 and the equivalent circuit. A typical application where this information may be useful is when designing an interface filter between the AD9773 and the Analog Devices AD8345 quadrature modulator ...
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... OPT required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9773 and the op amp, is also used to level shift the differential output of the AD9773 to midsupply (for example, AVDD/2). INTERFACING THE AD9773 WITH THE AD8345 ...
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... PLL enabled and disabled. Refer to Figure 105 through Figure 114, the schematics, and the layout for the AD9773 evaluation board for the jumper locations described below. The AD9773 outputs can be configured for various applications by referring to the following instructions ...
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... TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 102. Test Configuration for AD9773 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate ...
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... AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. FOR MORE INFORMATION, SEE THE TWO-PORT DATA INPUT MODE SECTION. Figure 103. Test Configuration for AD9773 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, INPUT CLOCK NOTES 1 ...
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... RC0603 G2 ENBL G3 VPS1 VOUT LOIP VPS2 LOIN G4A G1B G4B G1A QBBN IBBN QBBP IBBP ADTL1-12 CC0603 Figure 105. AD8345 Circuitry on AD9773 Evaluation Board Rev Page RC0603 ADTL1-12 CC0805 AD9773 ...
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... AD9773 CC0603 RC0603 CC0603 RC1206 CC0603 RC0603 CC0605 Figure 106. AD9773 Clock, Power Supplies, and Output Circuitry Rev Page CC0805 ...
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... Figure 107. AD9773 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev Page AD9773 ...
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... AD9773 Figure 108. AD9773 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev Page ...
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... Figure 109. AD9773 Evaluation Board Components, Top Side Figure 110. AD9773 Evaluation Board Components, Bottom Side Rev Page AD9773 ...
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... AD9773 Figure 112. AD9773 Evaluation Board Layout, Layer Two (Ground Plane) Figure 111. AD9773 Evaluation Board Layout, Layer One (Top) Rev Page ...
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... Figure 113. AD9773 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9773 Evaluation Board Layout, Layer Four (Bottom) Rev Page AD9773 ...
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... MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9773BSV −40°C to +85°C AD9773BSVRL −40°C to +85°C AD9773BSVZ 1 −40°C to +85°C 1 AD9773BSVZRL −40°C to +85°C AD9773- RoHS Compliant Part. 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ MAX 11. ...
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... NOTES Rev Page AD9773 ...
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... AD9773 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02857-0-10/07(D) Rev Page ...